1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/microch 4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Microchip Sparx5 Ethernet switch contro 7 title: Microchip Sparx5 Ethernet switch controller
8 8
9 maintainers: 9 maintainers:
10 - Steen Hegelund <steen.hegelund@microchip.co 10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com> 11 - Lars Povlsen <lars.povlsen@microchip.com>
12 12
13 description: | 13 description: |
14 The SparX-5 Enterprise Ethernet switch famil 14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanc 15 Enterprise switching features such as advanced TCAM-based VLAN and
16 QoS processing enabling delivery of differen 16 QoS processing enabling delivery of differentiated services, and
17 security through TCAM-based frame processing 17 security through TCAM-based frame processing using versatile content
18 aware processor (VCAP). 18 aware processor (VCAP).
19 19
20 IPv4/IPv6 Layer 3 (L3) unicast and multicast 20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
21 with up to 18K IPv4/9K IPv6 unicast LPM entr 21 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
22 IPv6 (S,G) multicast groups. 22 IPv6 (S,G) multicast groups.
23 23
24 L3 security features include source guard an 24 L3 security features include source guard and reverse path
25 forwarding (uRPF) tasks. Additional L3 featu 25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
26 IP tunnels (IP over GRE/IP). 26 IP tunnels (IP over GRE/IP).
27 27
28 The SparX-5 switch family targets managed La 28 The SparX-5 switch family targets managed Layer 2 and Layer 3
29 equipment in SMB, SME, and Enterprise where 29 equipment in SMB, SME, and Enterprise where high port count
30 1G/2.5G/5G/10G switching with 10G/25G aggreg 30 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
31 31
32 properties: 32 properties:
33 $nodename: 33 $nodename:
34 pattern: "^switch@[0-9a-f]+$" 34 pattern: "^switch@[0-9a-f]+$"
35 35
36 compatible: 36 compatible:
37 const: microchip,sparx5-switch 37 const: microchip,sparx5-switch
38 38
39 reg: 39 reg:
40 items: 40 items:
41 - description: cpu target 41 - description: cpu target
42 - description: devices target 42 - description: devices target
43 - description: general control block tar 43 - description: general control block target
44 44
45 reg-names: 45 reg-names:
46 items: 46 items:
47 - const: cpu 47 - const: cpu
48 - const: devices 48 - const: devices
49 - const: gcb 49 - const: gcb
50 50
51 interrupts: 51 interrupts:
52 minItems: 1 52 minItems: 1
53 items: 53 items:
54 - description: register based extraction 54 - description: register based extraction
55 - description: frame dma based extractio 55 - description: frame dma based extraction
56 - description: ptp interrupt 56 - description: ptp interrupt
57 57
58 interrupt-names: 58 interrupt-names:
59 minItems: 1 59 minItems: 1
60 items: 60 items:
61 - const: xtr 61 - const: xtr
62 - const: fdma 62 - const: fdma
63 - const: ptp 63 - const: ptp
64 64
65 resets: 65 resets:
66 items: 66 items:
67 - description: Reset controller used for 67 - description: Reset controller used for switch core reset (soft reset)
68 68
69 reset-names: 69 reset-names:
70 items: 70 items:
71 - const: switch 71 - const: switch
72 72
73 mac-address: true 73 mac-address: true
74 74
75 ethernet-ports: 75 ethernet-ports:
76 type: object 76 type: object
77 additionalProperties: false 77 additionalProperties: false
78 78
79 properties: 79 properties:
80 '#address-cells': 80 '#address-cells':
81 const: 1 81 const: 1
82 '#size-cells': 82 '#size-cells':
83 const: 0 83 const: 0
84 84
85 patternProperties: 85 patternProperties:
86 "^port@[0-9a-f]+$": 86 "^port@[0-9a-f]+$":
87 $ref: /schemas/net/ethernet-controller 87 $ref: /schemas/net/ethernet-controller.yaml#
88 unevaluatedProperties: false 88 unevaluatedProperties: false
89 89
90 properties: 90 properties:
91 reg: 91 reg:
92 description: Switch port number 92 description: Switch port number
93 93
94 phys: 94 phys:
95 maxItems: 1 95 maxItems: 1
96 description: 96 description:
97 phandle of a Ethernet SerDes PHY 97 phandle of a Ethernet SerDes PHY. This defines which SerDes
98 instance will handle the Etherne 98 instance will handle the Ethernet traffic.
99 99
100 microchip,bandwidth: 100 microchip,bandwidth:
101 description: Specifies bandwidth i 101 description: Specifies bandwidth in Mbit/s allocated to the port.
102 $ref: /schemas/types.yaml#/definit !! 102 $ref: "/schemas/types.yaml#/definitions/uint32"
103 maximum: 25000 103 maximum: 25000
104 104
105 microchip,sd-sgpio: 105 microchip,sd-sgpio:
106 description: 106 description:
107 Index of the ports Signal Detect 107 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
108 This is optional, and only neede 108 This is optional, and only needed if the default used index is
109 is not correct. 109 is not correct.
110 $ref: /schemas/types.yaml#/definit !! 110 $ref: "/schemas/types.yaml#/definitions/uint32"
111 minimum: 0 111 minimum: 0
112 maximum: 383 112 maximum: 383
113 113
114 required: 114 required:
115 - reg 115 - reg
116 - phys 116 - phys
117 - phy-mode 117 - phy-mode
118 - microchip,bandwidth 118 - microchip,bandwidth
119 119
120 oneOf: 120 oneOf:
121 - required: 121 - required:
122 - phy-handle 122 - phy-handle
123 - required: 123 - required:
124 - sfp 124 - sfp
125 - managed 125 - managed
126 126
127 required: 127 required:
128 - compatible 128 - compatible
129 - reg 129 - reg
130 - reg-names 130 - reg-names
131 - interrupts 131 - interrupts
132 - interrupt-names 132 - interrupt-names
133 - ethernet-ports 133 - ethernet-ports
134 134
135 additionalProperties: false 135 additionalProperties: false
136 136
137 examples: 137 examples:
138 - | 138 - |
139 #include <dt-bindings/interrupt-controller 139 #include <dt-bindings/interrupt-controller/arm-gic.h>
140 switch: switch@600000000 { 140 switch: switch@600000000 {
141 compatible = "microchip,sparx5-switch"; 141 compatible = "microchip,sparx5-switch";
142 reg = <0 0x401000>, 142 reg = <0 0x401000>,
143 <0x10004000 0x7fc000>, 143 <0x10004000 0x7fc000>,
144 <0x11010000 0xaf0000>; 144 <0x11010000 0xaf0000>;
145 reg-names = "cpu", "devices", "gcb"; 145 reg-names = "cpu", "devices", "gcb";
146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_ 146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "xtr"; 147 interrupt-names = "xtr";
148 resets = <&reset 0>; 148 resets = <&reset 0>;
149 reset-names = "switch"; 149 reset-names = "switch";
150 ethernet-ports { 150 ethernet-ports {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <0>; 152 #size-cells = <0>;
153 153
154 port0: port@0 { 154 port0: port@0 {
155 reg = <0>; 155 reg = <0>;
156 microchip,bandwidth = <1000>; 156 microchip,bandwidth = <1000>;
157 phys = <&serdes 13>; 157 phys = <&serdes 13>;
158 phy-handle = <&phy0>; 158 phy-handle = <&phy0>;
159 phy-mode = "qsgmii"; 159 phy-mode = "qsgmii";
160 }; 160 };
161 /* ... */ 161 /* ... */
162 /* Then the 25G interfaces */ 162 /* Then the 25G interfaces */
163 port60: port@60 { 163 port60: port@60 {
164 reg = <60>; 164 reg = <60>;
165 microchip,bandwidth = <25000>; 165 microchip,bandwidth = <25000>;
166 phys = <&serdes 29>; 166 phys = <&serdes 29>;
167 phy-mode = "10gbase-r"; 167 phy-mode = "10gbase-r";
168 sfp = <&sfp_eth60>; 168 sfp = <&sfp_eth60>;
169 managed = "in-band-status"; 169 managed = "in-band-status";
170 microchip,sd-sgpio = <365>; 170 microchip,sd-sgpio = <365>;
171 }; 171 };
172 port61: port@61 { 172 port61: port@61 {
173 reg = <61>; 173 reg = <61>;
174 microchip,bandwidth = <25000>; 174 microchip,bandwidth = <25000>;
175 phys = <&serdes 30>; 175 phys = <&serdes 30>;
176 phy-mode = "10gbase-r"; 176 phy-mode = "10gbase-r";
177 sfp = <&sfp_eth61>; 177 sfp = <&sfp_eth61>;
178 managed = "in-band-status"; 178 managed = "in-band-status";
179 microchip,sd-sgpio = <369>; 179 microchip,sd-sgpio = <369>;
180 }; 180 };
181 port62: port@62 { 181 port62: port@62 {
182 reg = <62>; 182 reg = <62>;
183 microchip,bandwidth = <25000>; 183 microchip,bandwidth = <25000>;
184 phys = <&serdes 31>; 184 phys = <&serdes 31>;
185 phy-mode = "10gbase-r"; 185 phy-mode = "10gbase-r";
186 sfp = <&sfp_eth62>; 186 sfp = <&sfp_eth62>;
187 managed = "in-band-status"; 187 managed = "in-band-status";
188 microchip,sd-sgpio = <373>; 188 microchip,sd-sgpio = <373>;
189 }; 189 };
190 port63: port@63 { 190 port63: port@63 {
191 reg = <63>; 191 reg = <63>;
192 microchip,bandwidth = <25000>; 192 microchip,bandwidth = <25000>;
193 phys = <&serdes 32>; 193 phys = <&serdes 32>;
194 phy-mode = "10gbase-r"; 194 phy-mode = "10gbase-r";
195 sfp = <&sfp_eth63>; 195 sfp = <&sfp_eth63>;
196 managed = "in-band-status"; 196 managed = "in-band-status";
197 microchip,sd-sgpio = <377>; 197 microchip,sd-sgpio = <377>;
198 }; 198 };
199 /* Finally the Management interface */ 199 /* Finally the Management interface */
200 port64: port@64 { 200 port64: port@64 {
201 reg = <64>; 201 reg = <64>;
202 microchip,bandwidth = <1000>; 202 microchip,bandwidth = <1000>;
203 phys = <&serdes 0>; 203 phys = <&serdes 0>;
204 phy-handle = <&phy64>; 204 phy-handle = <&phy64>;
205 phy-mode = "sgmii"; 205 phy-mode = "sgmii";
206 mac-address = [ 00 00 00 01 02 03 ]; 206 mac-address = [ 00 00 00 01 02 03 ];
207 }; 207 };
208 }; 208 };
209 }; 209 };
210 210
211 ... 211 ...
212 # vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft= 212 # vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
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