1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/mscc,mi 4 $id: http://devicetree.org/schemas/net/mscc,miim.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Microsemi MII Management Controller (MI 7 title: Microsemi MII Management Controller (MIIM)
8 8
9 maintainers: 9 maintainers:
10 - Alexandre Belloni <alexandre.belloni@bootli 10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 11
12 allOf: 12 allOf:
13 - $ref: mdio.yaml# 13 - $ref: mdio.yaml#
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 enum: 17 enum:
18 - mscc,ocelot-miim 18 - mscc,ocelot-miim
19 - microchip,lan966x-miim 19 - microchip,lan966x-miim
20 20
21 "#address-cells": 21 "#address-cells":
22 const: 1 22 const: 1
23 23
24 "#size-cells": 24 "#size-cells":
25 const: 0 25 const: 0
26 26
27 reg: 27 reg:
28 items: 28 items:
29 - description: base address 29 - description: base address
30 - description: associated reset register 30 - description: associated reset register for internal PHYs
31 minItems: 1 31 minItems: 1
32 32
33 interrupts: 33 interrupts:
34 maxItems: 1 34 maxItems: 1
35 35
36 clocks: 36 clocks:
37 maxItems: 1 37 maxItems: 1
38 38
39 clock-frequency: true 39 clock-frequency: true
40 40
41 resets: 41 resets:
42 items: 42 items:
43 - description: 43 - description:
44 Reset shared with all blocks attache 44 Reset shared with all blocks attached to the Switch Core Register
45 Bus (CSR) including VRAP slave. 45 Bus (CSR) including VRAP slave.
46 46
47 reset-names: 47 reset-names:
48 items: 48 items:
49 - const: switch 49 - const: switch
50 50
51 required: 51 required:
52 - compatible 52 - compatible
53 - reg 53 - reg
54 - "#address-cells" 54 - "#address-cells"
55 - "#size-cells" 55 - "#size-cells"
56 56
57 unevaluatedProperties: false 57 unevaluatedProperties: false
58 58
59 examples: 59 examples:
60 - | 60 - |
61 mdio@107009c { 61 mdio@107009c {
62 compatible = "mscc,ocelot-miim"; 62 compatible = "mscc,ocelot-miim";
63 reg = <0x107009c 0x36>, <0x10700f0 0x8>; 63 reg = <0x107009c 0x36>, <0x10700f0 0x8>;
64 interrupts = <14>; 64 interrupts = <14>;
65 #address-cells = <1>; 65 #address-cells = <1>;
66 #size-cells = <0>; 66 #size-cells = <0>;
67 67
68 phy0: ethernet-phy@0 { 68 phy0: ethernet-phy@0 {
69 reg = <0>; 69 reg = <0>;
70 }; 70 };
71 }; 71 };
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