1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/qca,ar7 4 $id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: QCA AR71XX MAC 7 title: QCA AR71XX MAC
8 8
9 allOf: 9 allOf:
10 - $ref: ethernet-controller.yaml# 10 - $ref: ethernet-controller.yaml#
11 11
12 maintainers: 12 maintainers:
13 - Oleksij Rempel <o.rempel@pengutronix.de> 13 - Oleksij Rempel <o.rempel@pengutronix.de>
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - items: 18 - items:
19 - enum: 19 - enum:
20 - qca,ar7100-eth # Atheros AR7 20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7 21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7 22 - qca,ar7241-eth # Atheros AR7241
23 - qca,ar7242-eth # Atheros AR7 23 - qca,ar7242-eth # Atheros AR7242
24 - qca,ar9130-eth # Atheros AR9 24 - qca,ar9130-eth # Atheros AR9130
25 - qca,ar9330-eth # Atheros AR9 25 - qca,ar9330-eth # Atheros AR9330
26 - qca,ar9340-eth # Atheros AR9 26 - qca,ar9340-eth # Atheros AR9340
27 - qca,qca9530-eth # Qualcomm At 27 - qca,qca9530-eth # Qualcomm Atheros QCA9530
28 - qca,qca9550-eth # Qualcomm At 28 - qca,qca9550-eth # Qualcomm Atheros QCA9550
29 - qca,qca9560-eth # Qualcomm At 29 - qca,qca9560-eth # Qualcomm Atheros QCA9560
30 30
31 reg: 31 reg:
32 maxItems: 1 32 maxItems: 1
33 33
34 interrupts: 34 interrupts:
35 maxItems: 1 35 maxItems: 1
36 36
>> 37 '#address-cells':
>> 38 description: number of address cells for the MDIO bus
>> 39 const: 1
>> 40
>> 41 '#size-cells':
>> 42 description: number of size cells on the MDIO bus
>> 43 const: 0
>> 44
37 clocks: 45 clocks:
38 items: 46 items:
39 - description: MAC main clock 47 - description: MAC main clock
40 - description: MDIO clock 48 - description: MDIO clock
41 49
42 clock-names: 50 clock-names:
43 items: 51 items:
44 - const: eth 52 - const: eth
45 - const: mdio 53 - const: mdio
46 54
47 resets: 55 resets:
48 items: 56 items:
49 - description: MAC reset 57 - description: MAC reset
50 - description: MDIO reset 58 - description: MDIO reset
51 59
52 reset-names: 60 reset-names:
53 items: 61 items:
54 - const: mac 62 - const: mac
55 - const: mdio 63 - const: mdio
56 64
57 mdio: <<
58 $ref: mdio.yaml# <<
59 unevaluatedProperties: false <<
60 <<
61 required: 65 required:
62 - compatible 66 - compatible
63 - reg 67 - reg
64 - interrupts 68 - interrupts
65 - phy-mode 69 - phy-mode
66 - clocks 70 - clocks
67 - clock-names 71 - clock-names
68 - resets 72 - resets
69 - reset-names 73 - reset-names
70 74
71 unevaluatedProperties: false 75 unevaluatedProperties: false
72 76
73 examples: 77 examples:
74 # Lager board 78 # Lager board
75 - | 79 - |
76 eth0: ethernet@19000000 { 80 eth0: ethernet@19000000 {
77 compatible = "qca,ar9330-eth"; 81 compatible = "qca,ar9330-eth";
78 reg = <0x19000000 0x200>; 82 reg = <0x19000000 0x200>;
79 interrupts = <4>; 83 interrupts = <4>;
80 resets = <&rst 9>, <&rst 22>; 84 resets = <&rst 9>, <&rst 22>;
81 reset-names = "mac", "mdio"; 85 reset-names = "mac", "mdio";
82 clocks = <&pll 1>, <&pll 2>; 86 clocks = <&pll 1>, <&pll 2>;
83 clock-names = "eth", "mdio"; 87 clock-names = "eth", "mdio";
>> 88 qca,ethcfg = <ðcfg>;
84 phy-mode = "mii"; 89 phy-mode = "mii";
85 phy-handle = <&phy_port4>; 90 phy-handle = <&phy_port4>;
86 }; 91 };
87 92
88 eth1: ethernet@1a000000 { 93 eth1: ethernet@1a000000 {
89 compatible = "qca,ar9330-eth"; 94 compatible = "qca,ar9330-eth";
90 reg = <0x1a000000 0x200>; 95 reg = <0x1a000000 0x200>;
91 interrupts = <5>; 96 interrupts = <5>;
92 resets = <&rst 13>, <&rst 23>; 97 resets = <&rst 13>, <&rst 23>;
93 reset-names = "mac", "mdio"; 98 reset-names = "mac", "mdio";
94 clocks = <&pll 1>, <&pll 2>; 99 clocks = <&pll 1>, <&pll 2>;
95 clock-names = "eth", "mdio"; 100 clock-names = "eth", "mdio";
96 101
97 phy-mode = "gmii"; 102 phy-mode = "gmii";
98 103
99 fixed-link { 104 fixed-link {
100 speed = <1000>; 105 speed = <1000>;
101 full-duplex; 106 full-duplex;
102 }; 107 };
103 108
104 mdio { 109 mdio {
105 #address-cells = <1>; 110 #address-cells = <1>;
106 #size-cells = <0>; 111 #size-cells = <0>;
107 112
108 switch10: switch@10 { 113 switch10: switch@10 {
>> 114 #address-cells = <1>;
>> 115 #size-cells = <0>;
>> 116
109 compatible = "qca,ar9331-switc 117 compatible = "qca,ar9331-switch";
110 reg = <0x10>; 118 reg = <0x10>;
111 resets = <&rst 8>; 119 resets = <&rst 8>;
112 reset-names = "switch"; 120 reset-names = "switch";
113 121
114 interrupt-parent = <&miscintc> 122 interrupt-parent = <&miscintc>;
115 interrupts = <12>; 123 interrupts = <12>;
116 124
117 interrupt-controller; 125 interrupt-controller;
118 #interrupt-cells = <1>; 126 #interrupt-cells = <1>;
119 127
120 ports { 128 ports {
121 #address-cells = <1>; 129 #address-cells = <1>;
122 #size-cells = <0>; 130 #size-cells = <0>;
123 131
124 switch_port0: port@0 { 132 switch_port0: port@0 {
125 reg = <0x0>; 133 reg = <0x0>;
>> 134 label = "cpu";
126 ethernet = <ð1>; 135 ethernet = <ð1>;
127 136
128 phy-mode = "gmii"; 137 phy-mode = "gmii";
129 138
130 fixed-link { 139 fixed-link {
131 speed = <1000>; 140 speed = <1000>;
132 full-duplex; 141 full-duplex;
133 }; 142 };
134 }; 143 };
135 144
136 switch_port1: port@1 { 145 switch_port1: port@1 {
137 reg = <0x1>; 146 reg = <0x1>;
138 phy-handle = <&phy_por 147 phy-handle = <&phy_port0>;
139 phy-mode = "internal"; 148 phy-mode = "internal";
140 }; 149 };
141 150
142 switch_port2: port@2 { 151 switch_port2: port@2 {
143 reg = <0x2>; 152 reg = <0x2>;
144 phy-handle = <&phy_por 153 phy-handle = <&phy_port1>;
145 phy-mode = "internal"; 154 phy-mode = "internal";
146 }; 155 };
147 156
148 switch_port3: port@3 { 157 switch_port3: port@3 {
149 reg = <0x3>; 158 reg = <0x3>;
150 phy-handle = <&phy_por 159 phy-handle = <&phy_port2>;
151 phy-mode = "internal"; 160 phy-mode = "internal";
152 }; 161 };
153 162
154 switch_port4: port@4 { 163 switch_port4: port@4 {
155 reg = <0x4>; 164 reg = <0x4>;
156 phy-handle = <&phy_por 165 phy-handle = <&phy_port3>;
157 phy-mode = "internal"; 166 phy-mode = "internal";
158 }; 167 };
159 }; 168 };
160 169
161 mdio { 170 mdio {
162 #address-cells = <1>; 171 #address-cells = <1>;
163 #size-cells = <0>; 172 #size-cells = <0>;
164 173
165 interrupt-parent = <&switc 174 interrupt-parent = <&switch10>;
166 175
167 phy_port0: ethernet-phy@0 176 phy_port0: ethernet-phy@0 {
168 reg = <0x0>; 177 reg = <0x0>;
169 interrupts = <0>; 178 interrupts = <0>;
170 }; 179 };
171 180
172 phy_port1: ethernet-phy@1 181 phy_port1: ethernet-phy@1 {
173 reg = <0x1>; 182 reg = <0x1>;
174 interrupts = <0>; 183 interrupts = <0>;
175 }; 184 };
176 185
177 phy_port2: ethernet-phy@2 186 phy_port2: ethernet-phy@2 {
178 reg = <0x2>; 187 reg = <0x2>;
179 interrupts = <0>; 188 interrupts = <0>;
180 }; 189 };
181 190
182 phy_port3: ethernet-phy@3 191 phy_port3: ethernet-phy@3 {
183 reg = <0x3>; 192 reg = <0x3>;
184 interrupts = <0>; 193 interrupts = <0>;
185 }; 194 };
186 195
187 phy_port4: ethernet-phy@4 196 phy_port4: ethernet-phy@4 {
188 reg = <0x4>; 197 reg = <0x4>;
189 interrupts = <0>; 198 interrupts = <0>;
190 }; 199 };
191 }; 200 };
192 }; 201 };
193 }; 202 };
194 }; 203 };
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