1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/qca,ar7 4 $id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: QCA AR71XX MAC 7 title: QCA AR71XX MAC
8 8
9 allOf: 9 allOf:
10 - $ref: ethernet-controller.yaml# 10 - $ref: ethernet-controller.yaml#
11 11
12 maintainers: 12 maintainers:
13 - Oleksij Rempel <o.rempel@pengutronix.de> 13 - Oleksij Rempel <o.rempel@pengutronix.de>
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - items: 18 - items:
19 - enum: 19 - enum:
20 - qca,ar7100-eth # Atheros AR7 20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7 21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7 22 - qca,ar7241-eth # Atheros AR7241
23 - qca,ar7242-eth # Atheros AR7 23 - qca,ar7242-eth # Atheros AR7242
24 - qca,ar9130-eth # Atheros AR9 24 - qca,ar9130-eth # Atheros AR9130
25 - qca,ar9330-eth # Atheros AR9 25 - qca,ar9330-eth # Atheros AR9330
26 - qca,ar9340-eth # Atheros AR9 26 - qca,ar9340-eth # Atheros AR9340
27 - qca,qca9530-eth # Qualcomm At 27 - qca,qca9530-eth # Qualcomm Atheros QCA9530
28 - qca,qca9550-eth # Qualcomm At 28 - qca,qca9550-eth # Qualcomm Atheros QCA9550
29 - qca,qca9560-eth # Qualcomm At 29 - qca,qca9560-eth # Qualcomm Atheros QCA9560
30 30
31 reg: 31 reg:
32 maxItems: 1 32 maxItems: 1
33 33
34 interrupts: 34 interrupts:
35 maxItems: 1 35 maxItems: 1
36 36
37 clocks: 37 clocks:
38 items: 38 items:
39 - description: MAC main clock 39 - description: MAC main clock
40 - description: MDIO clock 40 - description: MDIO clock
41 41
42 clock-names: 42 clock-names:
43 items: 43 items:
44 - const: eth 44 - const: eth
45 - const: mdio 45 - const: mdio
46 46
47 resets: 47 resets:
48 items: 48 items:
49 - description: MAC reset 49 - description: MAC reset
50 - description: MDIO reset 50 - description: MDIO reset
51 51
52 reset-names: 52 reset-names:
53 items: 53 items:
54 - const: mac 54 - const: mac
55 - const: mdio 55 - const: mdio
56 56
57 mdio: 57 mdio:
58 $ref: mdio.yaml# 58 $ref: mdio.yaml#
59 unevaluatedProperties: false 59 unevaluatedProperties: false
60 60
61 required: 61 required:
62 - compatible 62 - compatible
63 - reg 63 - reg
64 - interrupts 64 - interrupts
65 - phy-mode 65 - phy-mode
66 - clocks 66 - clocks
67 - clock-names 67 - clock-names
68 - resets 68 - resets
69 - reset-names 69 - reset-names
70 70
71 unevaluatedProperties: false 71 unevaluatedProperties: false
72 72
73 examples: 73 examples:
74 # Lager board 74 # Lager board
75 - | 75 - |
76 eth0: ethernet@19000000 { 76 eth0: ethernet@19000000 {
77 compatible = "qca,ar9330-eth"; 77 compatible = "qca,ar9330-eth";
78 reg = <0x19000000 0x200>; 78 reg = <0x19000000 0x200>;
79 interrupts = <4>; 79 interrupts = <4>;
80 resets = <&rst 9>, <&rst 22>; 80 resets = <&rst 9>, <&rst 22>;
81 reset-names = "mac", "mdio"; 81 reset-names = "mac", "mdio";
82 clocks = <&pll 1>, <&pll 2>; 82 clocks = <&pll 1>, <&pll 2>;
83 clock-names = "eth", "mdio"; 83 clock-names = "eth", "mdio";
84 phy-mode = "mii"; 84 phy-mode = "mii";
85 phy-handle = <&phy_port4>; 85 phy-handle = <&phy_port4>;
86 }; 86 };
87 87
88 eth1: ethernet@1a000000 { 88 eth1: ethernet@1a000000 {
89 compatible = "qca,ar9330-eth"; 89 compatible = "qca,ar9330-eth";
90 reg = <0x1a000000 0x200>; 90 reg = <0x1a000000 0x200>;
91 interrupts = <5>; 91 interrupts = <5>;
92 resets = <&rst 13>, <&rst 23>; 92 resets = <&rst 13>, <&rst 23>;
93 reset-names = "mac", "mdio"; 93 reset-names = "mac", "mdio";
94 clocks = <&pll 1>, <&pll 2>; 94 clocks = <&pll 1>, <&pll 2>;
95 clock-names = "eth", "mdio"; 95 clock-names = "eth", "mdio";
96 96
97 phy-mode = "gmii"; 97 phy-mode = "gmii";
98 98
99 fixed-link { 99 fixed-link {
100 speed = <1000>; 100 speed = <1000>;
101 full-duplex; 101 full-duplex;
102 }; 102 };
103 103
104 mdio { 104 mdio {
105 #address-cells = <1>; 105 #address-cells = <1>;
106 #size-cells = <0>; 106 #size-cells = <0>;
107 107
108 switch10: switch@10 { 108 switch10: switch@10 {
109 compatible = "qca,ar9331-switc 109 compatible = "qca,ar9331-switch";
110 reg = <0x10>; 110 reg = <0x10>;
111 resets = <&rst 8>; 111 resets = <&rst 8>;
112 reset-names = "switch"; 112 reset-names = "switch";
113 113
114 interrupt-parent = <&miscintc> 114 interrupt-parent = <&miscintc>;
115 interrupts = <12>; 115 interrupts = <12>;
116 116
117 interrupt-controller; 117 interrupt-controller;
118 #interrupt-cells = <1>; 118 #interrupt-cells = <1>;
119 119
120 ports { 120 ports {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <0>; 122 #size-cells = <0>;
123 123
124 switch_port0: port@0 { 124 switch_port0: port@0 {
125 reg = <0x0>; 125 reg = <0x0>;
126 ethernet = <ð1>; 126 ethernet = <ð1>;
127 127
128 phy-mode = "gmii"; 128 phy-mode = "gmii";
129 129
130 fixed-link { 130 fixed-link {
131 speed = <1000>; 131 speed = <1000>;
132 full-duplex; 132 full-duplex;
133 }; 133 };
134 }; 134 };
135 135
136 switch_port1: port@1 { 136 switch_port1: port@1 {
137 reg = <0x1>; 137 reg = <0x1>;
138 phy-handle = <&phy_por 138 phy-handle = <&phy_port0>;
139 phy-mode = "internal"; 139 phy-mode = "internal";
140 }; 140 };
141 141
142 switch_port2: port@2 { 142 switch_port2: port@2 {
143 reg = <0x2>; 143 reg = <0x2>;
144 phy-handle = <&phy_por 144 phy-handle = <&phy_port1>;
145 phy-mode = "internal"; 145 phy-mode = "internal";
146 }; 146 };
147 147
148 switch_port3: port@3 { 148 switch_port3: port@3 {
149 reg = <0x3>; 149 reg = <0x3>;
150 phy-handle = <&phy_por 150 phy-handle = <&phy_port2>;
151 phy-mode = "internal"; 151 phy-mode = "internal";
152 }; 152 };
153 153
154 switch_port4: port@4 { 154 switch_port4: port@4 {
155 reg = <0x4>; 155 reg = <0x4>;
156 phy-handle = <&phy_por 156 phy-handle = <&phy_port3>;
157 phy-mode = "internal"; 157 phy-mode = "internal";
158 }; 158 };
159 }; 159 };
160 160
161 mdio { 161 mdio {
162 #address-cells = <1>; 162 #address-cells = <1>;
163 #size-cells = <0>; 163 #size-cells = <0>;
164 164
165 interrupt-parent = <&switc 165 interrupt-parent = <&switch10>;
166 166
167 phy_port0: ethernet-phy@0 167 phy_port0: ethernet-phy@0 {
168 reg = <0x0>; 168 reg = <0x0>;
169 interrupts = <0>; 169 interrupts = <0>;
170 }; 170 };
171 171
172 phy_port1: ethernet-phy@1 172 phy_port1: ethernet-phy@1 {
173 reg = <0x1>; 173 reg = <0x1>;
174 interrupts = <0>; 174 interrupts = <0>;
175 }; 175 };
176 176
177 phy_port2: ethernet-phy@2 177 phy_port2: ethernet-phy@2 {
178 reg = <0x2>; 178 reg = <0x2>;
179 interrupts = <0>; 179 interrupts = <0>;
180 }; 180 };
181 181
182 phy_port3: ethernet-phy@3 182 phy_port3: ethernet-phy@3 {
183 reg = <0x3>; 183 reg = <0x3>;
184 interrupts = <0>; 184 interrupts = <0>;
185 }; 185 };
186 186
187 phy_port4: ethernet-phy@4 187 phy_port4: ethernet-phy@4 {
188 reg = <0x4>; 188 reg = <0x4>;
189 interrupts = <0>; 189 interrupts = <0>;
190 }; 190 };
191 }; 191 };
192 }; 192 };
193 }; 193 };
194 }; 194 };
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