1 * Synopsys DWC Ethernet QoS IP version 4.10 dr 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
2 2
3 This binding is deprecated, but it continues t <<
4 features should be preferably added to the stm <<
5 <<
6 This binding supports the Synopsys Designware 3 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
7 IP block. The IP supports multiple options for 4 IP block. The IP supports multiple options for bus type, clocking and reset
8 structure, and feature list. Consequently, a n 5 structure, and feature list. Consequently, a number of properties and list
9 entries in properties are marked as optional, 6 entries in properties are marked as optional, or only required in specific HW
10 configurations. 7 configurations.
11 8
12 Required properties: 9 Required properties:
13 - compatible: One of: 10 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-etherne 11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated int 12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethe 13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated int 14 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10" 15 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should 16 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-etherne 17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
21 compatible with earlier revisions of this 18 compatible with earlier revisions of this binding.
22 - reg: Address and length of the register set 19 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for eac 20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt. 21 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the foll 22 - clock-names: May contain any/all of the following depending on the IP
26 configuration, in any order: 23 configuration, in any order:
27 - "tx" 24 - "tx"
28 The EQOS transmit path clock. The HW signa 25 The EQOS transmit path clock. The HW signal name is clk_tx_i.
29 In some configurations (e.g. GMII/RGMII), 26 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
30 path. In other configurations, other clock 27 path. In other configurations, other clocks (such as tx_125, rmii) may
31 drive the PHY TX path. 28 drive the PHY TX path.
32 - "rx" 29 - "rx"
33 The EQOS receive path clock. The HW signal 30 The EQOS receive path clock. The HW signal name is clk_rx_i.
34 In some configurations (e.g. GMII/RGMII), 31 In some configurations (e.g. GMII/RGMII), this clock is derived from the
35 PHY's RX clock output. In other configurat 32 PHY's RX clock output. In other configurations, other clocks (such as
36 rx_125, rmii) may drive the EQOS RX path. 33 rx_125, rmii) may drive the EQOS RX path.
37 In cases where the PHY clock is directly f 34 In cases where the PHY clock is directly fed into the EQOS receive path
38 without intervening logic, the DT need not 35 without intervening logic, the DT need not represent this clock, since it
39 is assumed to be fully under the control o 36 is assumed to be fully under the control of the PHY device/driver. In
40 cases where SoC integration adds additiona 37 cases where SoC integration adds additional logic to this path, such as a
41 SW-controlled clock gate, this clock shoul 38 SW-controlled clock gate, this clock should be represented in DT.
42 - "slave_bus" 39 - "slave_bus"
43 The CPU/slave-bus (CSR) interface clock. T 40 The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
44 APB, AHB, AXI, etc. The HW signal name is 41 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
45 buses). 42 buses).
46 - "master_bus" 43 - "master_bus"
47 The master bus interface clock. Only requi 44 The master bus interface clock. Only required in configurations that use a
48 separate clock for the master and slave bu 45 separate clock for the master and slave bus interfaces. The HW signal name
49 is hclk_i (AHB) or aclk_i (AXI). 46 is hclk_i (AHB) or aclk_i (AXI).
50 - "ptp_ref" 47 - "ptp_ref"
51 The PTP reference clock. The HW signal nam 48 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
52 - "phy_ref_clk" 49 - "phy_ref_clk"
53 This clock is deprecated and should not be 50 This clock is deprecated and should not be used by new compatible values.
54 It is equivalent to "tx". 51 It is equivalent to "tx".
55 - "apb_pclk" 52 - "apb_pclk"
56 This clock is deprecated and should not be 53 This clock is deprecated and should not be used by new compatible values.
57 It is equivalent to "slave_bus". 54 It is equivalent to "slave_bus".
58 55
59 Note: Support for additional IP configuratio 56 Note: Support for additional IP configurations may require adding the
60 following clocks to this list in the future: 57 following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
61 clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk 58 clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
62 Configurations exist where multiple similar 59 Configurations exist where multiple similar clocks are used at once, e.g. all
63 of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i 60 of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
64 extend the binding with a separate clock-nam 61 extend the binding with a separate clock-names entry for each of those RX
65 clocks, rather than repurposing the existing 62 clocks, rather than repurposing the existing "rx" clock-names entry as a
66 generic/logical clock in a similar fashion t 63 generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
67 This will allow easy support for configurati 64 This will allow easy support for configurations that support multiple PHY
68 interfaces using a mux, and hence need to ha 65 interfaces using a mux, and hence need to have explicit control over
69 specific RX clocks. 66 specific RX clocks.
70 67
71 The following compatible values require the 68 The following compatible values require the following set of clocks:
72 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethe 69 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
73 - "slave_bus" 70 - "slave_bus"
74 - "master_bus" 71 - "master_bus"
75 - "rx" 72 - "rx"
76 - "tx" 73 - "tx"
77 - "ptp_ref" 74 - "ptp_ref"
78 - "axis,artpec6-eqos", "snps,dwc-qos-etherne 75 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
79 - "slave_bus" 76 - "slave_bus"
80 - "master_bus" 77 - "master_bus"
81 - "tx" 78 - "tx"
82 - "ptp_ref" 79 - "ptp_ref"
83 - "snps,dwc-qos-ethernet-4.10" (deprecated): 80 - "snps,dwc-qos-ethernet-4.10" (deprecated):
84 - "phy_ref_clk" 81 - "phy_ref_clk"
85 - "apb_clk" 82 - "apb_clk"
>> 83 - interrupt-parent: Should be the phandle for the interrupt controller
>> 84 that services interrupts for this device
86 - interrupts: Should contain the core's combin 85 - interrupts: Should contain the core's combined interrupt signal
87 - phy-mode: See ethernet.txt file in the same 86 - phy-mode: See ethernet.txt file in the same directory
88 - resets: Phandle and reset specifiers for eac 87 - resets: Phandle and reset specifiers for each entry in reset-names, in the
89 same order. See ../reset/reset.txt. 88 same order. See ../reset/reset.txt.
90 - reset-names: May contain any/all of the foll 89 - reset-names: May contain any/all of the following depending on the IP
91 configuration, in any order: 90 configuration, in any order:
92 - "eqos". The reset to the entire module. Th 91 - "eqos". The reset to the entire module. The HW signal name is hreset_n
93 (AHB) or aresetn_i (AXI). 92 (AHB) or aresetn_i (AXI).
94 93
95 The following compatible values require the 94 The following compatible values require the following set of resets:
96 (the reset properties may be omitted if empt 95 (the reset properties may be omitted if empty)
97 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethe 96 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
98 - "eqos". 97 - "eqos".
99 - "axis,artpec6-eqos", "snps,dwc-qos-etherne 98 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
100 - None. 99 - None.
101 - "snps,dwc-qos-ethernet-4.10" (deprecated): 100 - "snps,dwc-qos-ethernet-4.10" (deprecated):
102 - None. 101 - None.
103 102
104 Optional properties: 103 Optional properties:
105 - dma-coherent: Present if dma operations are 104 - dma-coherent: Present if dma operations are coherent
>> 105 - mac-address: See ethernet.txt in the same directory
>> 106 - local-mac-address: See ethernet.txt in the same directory
106 - phy-reset-gpios: Phandle and specifier for a 107 - phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
107 See ../gpio/gpio.txt. 108 See ../gpio/gpio.txt.
108 - snps,en-lpi: If present it enables use of th 109 - snps,en-lpi: If present it enables use of the AXI low-power interface
109 - snps,write-requests: Number of write request 110 - snps,write-requests: Number of write requests that the AXI port can issue.
110 It depends on the SoC configuration. 111 It depends on the SoC configuration.
111 - snps,read-requests: Number of read requests 112 - snps,read-requests: Number of read requests that the AXI port can issue.
112 It depends on the SoC configuration. 113 It depends on the SoC configuration.
113 - snps,burst-map: Bitmap of allowed AXI burst !! 114 - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
114 representing 4, then 8 etc. 115 representing 4, then 8 etc.
115 - snps,txpbl: DMA Programmable burst length fo 116 - snps,txpbl: DMA Programmable burst length for the TX DMA
116 - snps,rxpbl: DMA Programmable burst length fo 117 - snps,rxpbl: DMA Programmable burst length for the RX DMA
117 - snps,en-tx-lpi-clockgating: Enable gating of 118 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
118 TX low-power mode. 119 TX low-power mode.
119 - phy-handle: See ethernet.txt file in the sam 120 - phy-handle: See ethernet.txt file in the same directory
120 - mdio device tree subnode: When the GMAC has 121 - mdio device tree subnode: When the GMAC has a phy connected to its local
121 mdio, there must be device tree subnode wi 122 mdio, there must be device tree subnode with the following
122 required properties: 123 required properties:
123 - compatible: Must be "snps,dwc-qos-ethern 124 - compatible: Must be "snps,dwc-qos-ethernet-mdio".
124 - #address-cells: Must be <1>. 125 - #address-cells: Must be <1>.
125 - #size-cells: Must be <0>. 126 - #size-cells: Must be <0>.
126 127
127 For each phy on the mdio bus, there must b 128 For each phy on the mdio bus, there must be a node with the following
128 fields: 129 fields:
129 130
130 - reg: phy id used to communicate to phy. 131 - reg: phy id used to communicate to phy.
131 - device_type: Must be "ethernet-phy". 132 - device_type: Must be "ethernet-phy".
132 - fixed-mode device tree subnode: see fixe 133 - fixed-mode device tree subnode: see fixed-link.txt in the same directory
133 <<
134 The MAC address will be determined using the o <<
135 defined in ethernet.txt. <<
136 134
137 Examples: 135 Examples:
138 ethernet2@40010000 { 136 ethernet2@40010000 {
139 clock-names = "phy_ref_clk", "apb_pclk 137 clock-names = "phy_ref_clk", "apb_pclk";
140 clocks = <&clkc 17>, <&clkc 15>; 138 clocks = <&clkc 17>, <&clkc 15>;
141 compatible = "snps,dwc-qos-ethernet-4. 139 compatible = "snps,dwc-qos-ethernet-4.10";
142 interrupt-parent = <&intc>; 140 interrupt-parent = <&intc>;
143 interrupts = <0x0 0x1e 0x4>; 141 interrupts = <0x0 0x1e 0x4>;
144 reg = <0x40010000 0x4000>; 142 reg = <0x40010000 0x4000>;
145 phy-handle = <&phy2>; 143 phy-handle = <&phy2>;
146 phy-mode = "gmii"; 144 phy-mode = "gmii";
147 phy-reset-gpios = <&gpioctlr 43 GPIO_A 145 phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
148 146
149 snps,en-tx-lpi-clockgating; 147 snps,en-tx-lpi-clockgating;
150 snps,en-lpi; 148 snps,en-lpi;
151 snps,write-requests = <2>; 149 snps,write-requests = <2>;
152 snps,read-requests = <16>; 150 snps,read-requests = <16>;
153 snps,burst-map = <0x7>; 151 snps,burst-map = <0x7>;
154 snps,txpbl = <8>; 152 snps,txpbl = <8>;
155 snps,rxpbl = <2>; 153 snps,rxpbl = <2>;
156 154
157 dma-coherent; 155 dma-coherent;
158 156
159 mdio { 157 mdio {
160 #address-cells = <0x1>; 158 #address-cells = <0x1>;
161 #size-cells = <0x0>; 159 #size-cells = <0x0>;
162 phy2: phy@1 { 160 phy2: phy@1 {
163 compatible = "ethernet 161 compatible = "ethernet-phy-ieee802.3-c22";
164 device_type = "etherne 162 device_type = "ethernet-phy";
165 reg = <0x1>; 163 reg = <0x1>;
166 }; 164 };
167 }; 165 };
168 }; 166 };
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