1 * Synopsys DWC Ethernet QoS IP version 4.10 dr 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
2 2
3 This binding is deprecated, but it continues t <<
4 features should be preferably added to the stm <<
5 <<
6 This binding supports the Synopsys Designware <<
7 IP block. The IP supports multiple options for <<
8 structure, and feature list. Consequently, a n <<
9 entries in properties are marked as optional, <<
10 configurations. <<
11 3
12 Required properties: 4 Required properties:
13 - compatible: One of: !! 5 - compatible: Should be "snps,dwc-qos-ethernet-4.10"
14 - "axis,artpec6-eqos", "snps,dwc-qos-etherne <<
15 Represents the IP core when integrated int <<
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethe <<
17 Represents the IP core when integrated int <<
18 - "snps,dwc-qos-ethernet-4.10" <<
19 This combination is deprecated. It should <<
20 "axis,artpec6-eqos", "snps,dwc-qos-etherne <<
21 compatible with earlier revisions of this <<
22 - reg: Address and length of the register set 6 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for eac !! 7 - clocks: Phandles to the reference clock and the bus clock
24 same order. See ../clock/clock-bindings.txt. !! 8 - clock-names: Should be "phy_ref_clk" for the reference clock and "apb_pclk"
25 - clock-names: May contain any/all of the foll !! 9 for the bus clock.
26 configuration, in any order: !! 10 - interrupt-parent: Should be the phandle for the interrupt controller
27 - "tx" !! 11 that services interrupts for this device
28 The EQOS transmit path clock. The HW signa <<
29 In some configurations (e.g. GMII/RGMII), <<
30 path. In other configurations, other clock <<
31 drive the PHY TX path. <<
32 - "rx" <<
33 The EQOS receive path clock. The HW signal <<
34 In some configurations (e.g. GMII/RGMII), <<
35 PHY's RX clock output. In other configurat <<
36 rx_125, rmii) may drive the EQOS RX path. <<
37 In cases where the PHY clock is directly f <<
38 without intervening logic, the DT need not <<
39 is assumed to be fully under the control o <<
40 cases where SoC integration adds additiona <<
41 SW-controlled clock gate, this clock shoul <<
42 - "slave_bus" <<
43 The CPU/slave-bus (CSR) interface clock. T <<
44 APB, AHB, AXI, etc. The HW signal name is <<
45 buses). <<
46 - "master_bus" <<
47 The master bus interface clock. Only requi <<
48 separate clock for the master and slave bu <<
49 is hclk_i (AHB) or aclk_i (AXI). <<
50 - "ptp_ref" <<
51 The PTP reference clock. The HW signal nam <<
52 - "phy_ref_clk" <<
53 This clock is deprecated and should not be <<
54 It is equivalent to "tx". <<
55 - "apb_pclk" <<
56 This clock is deprecated and should not be <<
57 It is equivalent to "slave_bus". <<
58 <<
59 Note: Support for additional IP configuratio <<
60 following clocks to this list in the future: <<
61 clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk <<
62 Configurations exist where multiple similar <<
63 of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i <<
64 extend the binding with a separate clock-nam <<
65 clocks, rather than repurposing the existing <<
66 generic/logical clock in a similar fashion t <<
67 This will allow easy support for configurati <<
68 interfaces using a mux, and hence need to ha <<
69 specific RX clocks. <<
70 <<
71 The following compatible values require the <<
72 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethe <<
73 - "slave_bus" <<
74 - "master_bus" <<
75 - "rx" <<
76 - "tx" <<
77 - "ptp_ref" <<
78 - "axis,artpec6-eqos", "snps,dwc-qos-etherne <<
79 - "slave_bus" <<
80 - "master_bus" <<
81 - "tx" <<
82 - "ptp_ref" <<
83 - "snps,dwc-qos-ethernet-4.10" (deprecated): <<
84 - "phy_ref_clk" <<
85 - "apb_clk" <<
86 - interrupts: Should contain the core's combin 12 - interrupts: Should contain the core's combined interrupt signal
87 - phy-mode: See ethernet.txt file in the same 13 - phy-mode: See ethernet.txt file in the same directory
88 - resets: Phandle and reset specifiers for eac <<
89 same order. See ../reset/reset.txt. <<
90 - reset-names: May contain any/all of the foll <<
91 configuration, in any order: <<
92 - "eqos". The reset to the entire module. Th <<
93 (AHB) or aresetn_i (AXI). <<
94 <<
95 The following compatible values require the <<
96 (the reset properties may be omitted if empt <<
97 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethe <<
98 - "eqos". <<
99 - "axis,artpec6-eqos", "snps,dwc-qos-etherne <<
100 - None. <<
101 - "snps,dwc-qos-ethernet-4.10" (deprecated): <<
102 - None. <<
103 14
104 Optional properties: 15 Optional properties:
105 - dma-coherent: Present if dma operations are 16 - dma-coherent: Present if dma operations are coherent
106 - phy-reset-gpios: Phandle and specifier for a !! 17 - mac-address: See ethernet.txt in the same directory
107 See ../gpio/gpio.txt. !! 18 - local-mac-address: See ethernet.txt in the same directory
108 - snps,en-lpi: If present it enables use of th 19 - snps,en-lpi: If present it enables use of the AXI low-power interface
109 - snps,write-requests: Number of write request 20 - snps,write-requests: Number of write requests that the AXI port can issue.
110 It depends on the SoC configuration. 21 It depends on the SoC configuration.
111 - snps,read-requests: Number of read requests 22 - snps,read-requests: Number of read requests that the AXI port can issue.
112 It depends on the SoC configuration. 23 It depends on the SoC configuration.
113 - snps,burst-map: Bitmap of allowed AXI burst !! 24 - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
114 representing 4, then 8 etc. 25 representing 4, then 8 etc.
115 - snps,txpbl: DMA Programmable burst length fo 26 - snps,txpbl: DMA Programmable burst length for the TX DMA
116 - snps,rxpbl: DMA Programmable burst length fo 27 - snps,rxpbl: DMA Programmable burst length for the RX DMA
117 - snps,en-tx-lpi-clockgating: Enable gating of 28 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
118 TX low-power mode. 29 TX low-power mode.
119 - phy-handle: See ethernet.txt file in the sam 30 - phy-handle: See ethernet.txt file in the same directory
120 - mdio device tree subnode: When the GMAC has 31 - mdio device tree subnode: When the GMAC has a phy connected to its local
121 mdio, there must be device tree subnode wi 32 mdio, there must be device tree subnode with the following
122 required properties: 33 required properties:
123 - compatible: Must be "snps,dwc-qos-ethern 34 - compatible: Must be "snps,dwc-qos-ethernet-mdio".
124 - #address-cells: Must be <1>. 35 - #address-cells: Must be <1>.
125 - #size-cells: Must be <0>. 36 - #size-cells: Must be <0>.
126 37
127 For each phy on the mdio bus, there must b 38 For each phy on the mdio bus, there must be a node with the following
128 fields: 39 fields:
129 40
130 - reg: phy id used to communicate to phy. 41 - reg: phy id used to communicate to phy.
131 - device_type: Must be "ethernet-phy". 42 - device_type: Must be "ethernet-phy".
132 - fixed-mode device tree subnode: see fixe 43 - fixed-mode device tree subnode: see fixed-link.txt in the same directory
133 44
134 The MAC address will be determined using the o <<
135 defined in ethernet.txt. <<
136 <<
137 Examples: 45 Examples:
138 ethernet2@40010000 { 46 ethernet2@40010000 {
139 clock-names = "phy_ref_clk", "apb_pclk 47 clock-names = "phy_ref_clk", "apb_pclk";
140 clocks = <&clkc 17>, <&clkc 15>; 48 clocks = <&clkc 17>, <&clkc 15>;
141 compatible = "snps,dwc-qos-ethernet-4. 49 compatible = "snps,dwc-qos-ethernet-4.10";
142 interrupt-parent = <&intc>; 50 interrupt-parent = <&intc>;
143 interrupts = <0x0 0x1e 0x4>; 51 interrupts = <0x0 0x1e 0x4>;
144 reg = <0x40010000 0x4000>; 52 reg = <0x40010000 0x4000>;
145 phy-handle = <&phy2>; 53 phy-handle = <&phy2>;
146 phy-mode = "gmii"; 54 phy-mode = "gmii";
147 phy-reset-gpios = <&gpioctlr 43 GPIO_A <<
148 55
149 snps,en-tx-lpi-clockgating; 56 snps,en-tx-lpi-clockgating;
150 snps,en-lpi; 57 snps,en-lpi;
151 snps,write-requests = <2>; 58 snps,write-requests = <2>;
152 snps,read-requests = <16>; 59 snps,read-requests = <16>;
153 snps,burst-map = <0x7>; 60 snps,burst-map = <0x7>;
154 snps,txpbl = <8>; 61 snps,txpbl = <8>;
155 snps,rxpbl = <2>; 62 snps,rxpbl = <2>;
156 63
157 dma-coherent; 64 dma-coherent;
158 65
159 mdio { 66 mdio {
160 #address-cells = <0x1>; 67 #address-cells = <0x1>;
161 #size-cells = <0x0>; 68 #size-cells = <0x0>;
162 phy2: phy@1 { 69 phy2: phy@1 {
163 compatible = "ethernet 70 compatible = "ethernet-phy-ieee802.3-c22";
164 device_type = "etherne 71 device_type = "ethernet-phy";
165 reg = <0x1>; 72 reg = <0x1>;
166 }; 73 };
167 }; 74 };
168 }; 75 };
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