1 Altera SOCFPGA SoC DWMAC controller 1 Altera SOCFPGA SoC DWMAC controller
2 2
3 This is a variant of the dwmac/stmmac driver a 3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
4 present in Documentation/devicetree/bindings/n 4 present in Documentation/devicetree/bindings/net/stmmac.txt.
5 5
6 The device node has additional properties: 6 The device node has additional properties:
7 7
8 Required properties: 8 Required properties:
9 - compatible : For Cyclone5/Arria5 SoCs it 9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For A 10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10 11 "altr,socfpga-stmmac-a10-s10".
12 Along with "snps,dwmac" and 12 Along with "snps,dwmac" and any applicable more detailed
13 designware version numbers d 13 designware version numbers documented in stmmac.txt
14 - altr,sysmgr-syscon : Should be the phandle 14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
15 encompasses the glue register, the register 15 encompasses the glue register, the register offset, and the register shift.
16 On Cyclone5/Arria5, the register shift repr 16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
17 on the Arria10/Stratix10/Agilex platforms, 17 on the Arria10/Stratix10/Agilex platforms, the register shift represents
18 bit for each emac to enable/disable signals 18 bit for each emac to enable/disable signals from the FPGA fabric to the
19 EMAC modules. 19 EMAC modules.
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk in 20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
21 for ptp ref clk. This affects all emacs as 21 for ptp ref clk. This affects all emacs as the clock is common.
22 22
23 Optional properties: 23 Optional properties:
24 altr,emac-splitter: Should be the phandle to t 24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected 25 DWMAC controller is connected emac splitter.
26 phy-mode: The phy mode the ethernet operates i 26 phy-mode: The phy mode the ethernet operates in
27 altr,sgmii-to-sgmii-converter: phandle to the 27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
28 28
29 This device node has additional phandle depend 29 This device node has additional phandle dependency, the sgmii converter:
30 30
31 Required properties: 31 Required properties:
32 - compatible : Should be altr,gmii-to-sgmii 32 - compatible : Should be altr,gmii-to-sgmii-2.0
33 - reg-names : Should be "eth_tse_control_p 33 - reg-names : Should be "eth_tse_control_port"
34 34
35 Example: 35 Example:
36 36
37 gmii_to_sgmii_converter: phy@100000240 { 37 gmii_to_sgmii_converter: phy@100000240 {
38 compatible = "altr,gmii-to-sgmii-2.0"; 38 compatible = "altr,gmii-to-sgmii-2.0";
39 reg = <0x00000001 0x00000240 0x0000000 39 reg = <0x00000001 0x00000240 0x00000008>,
40 <0x00000001 0x00000200 0x00000 40 <0x00000001 0x00000200 0x00000040>;
41 reg-names = "eth_tse_control_port"; 41 reg-names = "eth_tse_control_port";
42 clocks = <&sgmii_1_clk_0 &emac1 1 &sgm 42 clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
43 clock-names = "tse_pcs_ref_clk_clock_c 43 clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
44 }; 44 };
45 45
46 gmac0: ethernet@ff700000 { 46 gmac0: ethernet@ff700000 {
47 compatible = "altr,socfpga-stmmac", "s 47 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
48 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 48 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
49 reg = <0xff700000 0x2000>; 49 reg = <0xff700000 0x2000>;
50 interrupts = <0 115 4>; 50 interrupts = <0 115 4>;
51 interrupt-names = "macirq"; 51 interrupt-names = "macirq";
52 mac-address = [00 00 00 00 00 00];/* F 52 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
53 clocks = <&emac_0_clk>; 53 clocks = <&emac_0_clk>;
54 clock-names = "stmmaceth"; 54 clock-names = "stmmaceth";
55 phy-mode = "sgmii"; 55 phy-mode = "sgmii";
56 altr,gmii-to-sgmii-converter = <&gmii_ 56 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
57 }; 57 };
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