1 Altera SOCFPGA SoC DWMAC controller
2
3 This is a variant of the dwmac/stmmac driver a
4 present in Documentation/devicetree/bindings/n
5
6 The device node has additional properties:
7
8 Required properties:
9 - compatible : For Cyclone5/Arria5 SoCs it
10 "altr,socfpga-stmmac". For A
11 "altr,socfpga-stmmac-a10-s10
12 Along with "snps,dwmac" and
13 designware version numbers d
14 - altr,sysmgr-syscon : Should be the phandle
15 encompasses the glue register, the register
16 On Cyclone5/Arria5, the register shift repr
17 on the Arria10/Stratix10/Agilex platforms,
18 bit for each emac to enable/disable signals
19 EMAC modules.
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk in
21 for ptp ref clk. This affects all emacs as
22
23 Optional properties:
24 altr,emac-splitter: Should be the phandle to t
25 DWMAC controller is connected
26 phy-mode: The phy mode the ethernet operates i
27 altr,sgmii-to-sgmii-converter: phandle to the
28
29 This device node has additional phandle depend
30
31 Required properties:
32 - compatible : Should be altr,gmii-to-sgmii
33 - reg-names : Should be "eth_tse_control_p
34
35 Example:
36
37 gmii_to_sgmii_converter: phy@100000240 {
38 compatible = "altr,gmii-to-sgmii-2.0";
39 reg = <0x00000001 0x00000240 0x0000000
40 <0x00000001 0x00000200 0x00000
41 reg-names = "eth_tse_control_port";
42 clocks = <&sgmii_1_clk_0 &emac1 1 &sgm
43 clock-names = "tse_pcs_ref_clk_clock_c
44 };
45
46 gmac0: ethernet@ff700000 {
47 compatible = "altr,socfpga-stmmac", "s
48 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
49 reg = <0xff700000 0x2000>;
50 interrupts = <0 115 4>;
51 interrupt-names = "macirq";
52 mac-address = [00 00 00 00 00 00];/* F
53 clocks = <&emac_0_clk>;
54 clock-names = "stmmaceth";
55 phy-mode = "sgmii";
56 altr,gmii-to-sgmii-converter = <&gmii_
57 };
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