1 Altera SOCFPGA SoC DWMAC controller 1 Altera SOCFPGA SoC DWMAC controller
2 2
3 This is a variant of the dwmac/stmmac driver a 3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
4 present in Documentation/devicetree/bindings/n 4 present in Documentation/devicetree/bindings/net/stmmac.txt.
5 5
6 The device node has additional properties: 6 The device node has additional properties:
7 7
8 Required properties: 8 Required properties:
9 - compatible : For Cyclone5/Arria5 SoCs it !! 9 - compatible : Should contain "altr,socfpga-stmmac" along with
10 "altr,socfpga-stmmac". For A !! 10 "snps,dwmac" and any applicable more detailed
11 "altr,socfpga-stmmac-a10-s10 <<
12 Along with "snps,dwmac" and <<
13 designware version numbers d 11 designware version numbers documented in stmmac.txt
14 - altr,sysmgr-syscon : Should be the phandle 12 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
15 encompasses the glue register, the register 13 encompasses the glue register, the register offset, and the register shift.
16 On Cyclone5/Arria5, the register shift repr <<
17 on the Arria10/Stratix10/Agilex platforms, <<
18 bit for each emac to enable/disable signals <<
19 EMAC modules. <<
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk in <<
21 for ptp ref clk. This affects all emacs as <<
22 14
23 Optional properties: 15 Optional properties:
24 altr,emac-splitter: Should be the phandle to t 16 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected 17 DWMAC controller is connected emac splitter.
26 phy-mode: The phy mode the ethernet operates i <<
27 altr,sgmii-to-sgmii-converter: phandle to the <<
28 <<
29 This device node has additional phandle depend <<
30 <<
31 Required properties: <<
32 - compatible : Should be altr,gmii-to-sgmii <<
33 - reg-names : Should be "eth_tse_control_p <<
34 18
35 Example: 19 Example:
36 20
37 gmii_to_sgmii_converter: phy@100000240 { <<
38 compatible = "altr,gmii-to-sgmii-2.0"; <<
39 reg = <0x00000001 0x00000240 0x0000000 <<
40 <0x00000001 0x00000200 0x00000 <<
41 reg-names = "eth_tse_control_port"; <<
42 clocks = <&sgmii_1_clk_0 &emac1 1 &sgm <<
43 clock-names = "tse_pcs_ref_clk_clock_c <<
44 }; <<
45 <<
46 gmac0: ethernet@ff700000 { 21 gmac0: ethernet@ff700000 {
47 compatible = "altr,socfpga-stmmac", "s 22 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
48 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 23 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
>> 24 status = "disabled";
49 reg = <0xff700000 0x2000>; 25 reg = <0xff700000 0x2000>;
50 interrupts = <0 115 4>; 26 interrupts = <0 115 4>;
51 interrupt-names = "macirq"; 27 interrupt-names = "macirq";
52 mac-address = [00 00 00 00 00 00];/* F 28 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
53 clocks = <&emac_0_clk>; 29 clocks = <&emac_0_clk>;
54 clock-names = "stmmaceth"; 30 clock-names = "stmmaceth";
55 phy-mode = "sgmii"; <<
56 altr,gmii-to-sgmii-converter = <&gmii_ <<
57 }; 31 };
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