1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw 4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: TI SoC Ethernet Switch Controller (CPSW !! 7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Siddharth Vadapalli <s-vadapalli@ti.com> !! 10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Roger Quadros <rogerq@kernel.org> !! 11 - Sekhar Nori <nsekhar@ti.com>
12 12
13 description: 13 description:
14 The 3-port switch gigabit ethernet subsystem 14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an et 15 communication and can be configured as an ethernet switch. It provides the
16 gigabit media independent interface (GMII),r 16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media 17 independent interface (RGMII), reduced media independent interface (RMII),
18 the management data input output (MDIO) for 18 the management data input output (MDIO) for physical layer device (PHY)
19 management. 19 management.
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 oneOf: 23 oneOf:
24 - const: ti,cpsw-switch 24 - const: ti,cpsw-switch
25 - items: 25 - items:
26 - const: ti,am335x-cpsw-switch 26 - const: ti,am335x-cpsw-switch
27 - const: ti,cpsw-switch 27 - const: ti,cpsw-switch
28 - items: 28 - items:
29 - const: ti,am4372-cpsw-switch 29 - const: ti,am4372-cpsw-switch
30 - const: ti,cpsw-switch 30 - const: ti,cpsw-switch
31 - items: 31 - items:
32 - const: ti,dra7-cpsw-switch 32 - const: ti,dra7-cpsw-switch
33 - const: ti,cpsw-switch 33 - const: ti,cpsw-switch
34 34
35 reg: 35 reg:
36 maxItems: 1 36 maxItems: 1
37 description: 37 description:
38 The physical base address and size of fu 38 The physical base address and size of full the CPSW module IO range
39 39
40 '#address-cells': 40 '#address-cells':
41 const: 1 41 const: 1
42 42
43 '#size-cells': 43 '#size-cells':
44 const: 1 44 const: 1
45 45
46 ranges: true 46 ranges: true
47 47
48 clocks: 48 clocks:
49 maxItems: 1 49 maxItems: 1
50 description: CPSW functional clock 50 description: CPSW functional clock
51 51
52 clock-names: 52 clock-names:
53 items: 53 items:
54 - const: fck 54 - const: fck
55 55
56 interrupts: 56 interrupts:
57 items: 57 items:
58 - description: RX_THRESH interrupt 58 - description: RX_THRESH interrupt
59 - description: RX interrupt 59 - description: RX interrupt
60 - description: TX interrupt 60 - description: TX interrupt
61 - description: MISC interrupt 61 - description: MISC interrupt
62 62
63 interrupt-names: 63 interrupt-names:
64 items: 64 items:
65 - const: rx_thresh !! 65 - const: "rx_thresh"
66 - const: rx !! 66 - const: "rx"
67 - const: tx !! 67 - const: "tx"
68 - const: misc !! 68 - const: "misc"
69 69
70 pinctrl-names: true 70 pinctrl-names: true
71 71
72 syscon: 72 syscon:
73 $ref: /schemas/types.yaml#/definitions/pha 73 $ref: /schemas/types.yaml#/definitions/phandle
74 description: 74 description:
75 Phandle to the system control device nod 75 Phandle to the system control device node which provides access to
76 efuse IO range with MAC addresses 76 efuse IO range with MAC addresses
77 77
78 ethernet-ports: 78 ethernet-ports:
79 type: object 79 type: object
80 additionalProperties: false <<
81 <<
82 properties: 80 properties:
83 '#address-cells': 81 '#address-cells':
84 const: 1 82 const: 1
85 '#size-cells': 83 '#size-cells':
86 const: 0 84 const: 0
87 85
88 patternProperties: 86 patternProperties:
89 "^port@[12]$": !! 87 "^port@[0-9]+$":
90 type: object 88 type: object
91 description: CPSW external ports 89 description: CPSW external ports
92 90
93 $ref: ethernet-controller.yaml# 91 $ref: ethernet-controller.yaml#
94 unevaluatedProperties: false <<
95 92
96 properties: 93 properties:
97 reg: 94 reg:
98 items: 95 items:
99 - enum: [1, 2] 96 - enum: [1, 2]
100 description: CPSW port number 97 description: CPSW port number
101 98
102 phys: 99 phys:
103 maxItems: 1 100 maxItems: 1
104 description: phandle on phy-gmii-s 101 description: phandle on phy-gmii-sel PHY
105 102
106 label: 103 label:
107 description: label associated with 104 description: label associated with this port
108 105
109 ti,dual-emac-pvid: 106 ti,dual-emac-pvid:
110 $ref: /schemas/types.yaml#/definit 107 $ref: /schemas/types.yaml#/definitions/uint32
111 minimum: 1 108 minimum: 1
112 maximum: 1024 109 maximum: 1024
113 description: 110 description:
114 Specifies default PORT VID to be 111 Specifies default PORT VID to be used to segregate
115 ports. Default value - CPSW port 112 ports. Default value - CPSW port number.
116 113
117 required: 114 required:
118 - reg 115 - reg
119 - phys 116 - phys
120 117
121 cpts: 118 cpts:
122 type: object 119 type: object
123 unevaluatedProperties: false <<
124 description: 120 description:
125 The Common Platform Time Sync (CPTS) mod 121 The Common Platform Time Sync (CPTS) module
126 122
127 properties: 123 properties:
128 clocks: 124 clocks:
129 maxItems: 1 125 maxItems: 1
130 description: CPTS reference clock 126 description: CPTS reference clock
131 127
132 clock-names: 128 clock-names:
133 items: 129 items:
134 - const: cpts 130 - const: cpts
135 131
136 cpts_clock_mult: 132 cpts_clock_mult:
137 $ref: /schemas/types.yaml#/definitions 133 $ref: /schemas/types.yaml#/definitions/uint32
138 description: 134 description:
139 Numerator to convert input clock tic 135 Numerator to convert input clock ticks into ns
140 136
141 cpts_clock_shift: 137 cpts_clock_shift:
142 $ref: /schemas/types.yaml#/definitions 138 $ref: /schemas/types.yaml#/definitions/uint32
143 description: 139 description:
144 Denominator to convert input clock t 140 Denominator to convert input clock ticks into ns.
145 Mult and shift will be calculated ba 141 Mult and shift will be calculated basing on CPTS rftclk frequency if
146 both cpts_clock_shift and cpts_clock 142 both cpts_clock_shift and cpts_clock_mult properties are not provided.
147 143
148 required: 144 required:
149 - clocks 145 - clocks
150 - clock-names 146 - clock-names
151 147
152 patternProperties: 148 patternProperties:
153 "^mdio@": 149 "^mdio@":
154 type: object 150 type: object
155 description: 151 description:
156 CPSW MDIO bus. 152 CPSW MDIO bus.
157 $ref: ti,davinci-mdio.yaml# !! 153 $ref: "ti,davinci-mdio.yaml#"
158 154
159 155
160 required: 156 required:
161 - compatible 157 - compatible
162 - reg 158 - reg
163 - ranges 159 - ranges
164 - clocks 160 - clocks
165 - clock-names 161 - clock-names
166 - interrupts 162 - interrupts
167 - interrupt-names 163 - interrupt-names
168 - '#address-cells' 164 - '#address-cells'
169 - '#size-cells' 165 - '#size-cells'
170 166
171 additionalProperties: false 167 additionalProperties: false
172 168
173 examples: 169 examples:
174 - | 170 - |
175 #include <dt-bindings/interrupt-controller 171 #include <dt-bindings/interrupt-controller/irq.h>
176 #include <dt-bindings/interrupt-controller 172 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/clock/dra7.h> 173 #include <dt-bindings/clock/dra7.h>
178 174
179 mac_sw: switch@0 { 175 mac_sw: switch@0 {
180 compatible = "ti,dra7-cpsw-switch","ti 176 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
181 reg = <0x0 0x4000>; 177 reg = <0x0 0x4000>;
182 ranges = <0 0 0x4000>; 178 ranges = <0 0 0x4000>;
183 clocks = <&gmac_main_clk>; 179 clocks = <&gmac_main_clk>;
184 clock-names = "fck"; 180 clock-names = "fck";
185 #address-cells = <1>; 181 #address-cells = <1>;
186 #size-cells = <1>; 182 #size-cells = <1>;
187 syscon = <&scm_conf>; 183 syscon = <&scm_conf>;
188 184
189 interrupts = <GIC_SPI 334 IRQ_TYPE_LEV 185 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 335 IRQ_TYPE_LEV 186 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 336 IRQ_TYPE_LEV 187 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 337 IRQ_TYPE_LEV 188 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
193 interrupt-names = "rx_thresh", "rx", " 189 interrupt-names = "rx_thresh", "rx", "tx", "misc";
194 190
195 ethernet-ports { 191 ethernet-ports {
196 #address-cells = <1>; 192 #address-cells = <1>;
197 #size-cells = <0>; 193 #size-cells = <0>;
198 194
199 cpsw_port1: port@1 { 195 cpsw_port1: port@1 {
200 reg = <1>; 196 reg = <1>;
201 label = "port1"; 197 label = "port1";
202 mac-address = [ 00 00 198 mac-address = [ 00 00 00 00 00 00 ];
203 phys = <&phy_gmii_sel 199 phys = <&phy_gmii_sel 1>;
204 phy-handle = <ðphy0 200 phy-handle = <ðphy0_sw>;
205 phy-mode = "rgmii"; 201 phy-mode = "rgmii";
206 ti,dual-emac-pvid = <1 202 ti,dual-emac-pvid = <1>;
207 }; 203 };
208 204
209 cpsw_port2: port@2 { 205 cpsw_port2: port@2 {
210 reg = <2>; 206 reg = <2>;
211 label = "wan"; 207 label = "wan";
212 mac-address = [ 00 00 208 mac-address = [ 00 00 00 00 00 00 ];
213 phys = <&phy_gmii_sel 209 phys = <&phy_gmii_sel 2>;
214 phy-handle = <ðphy1 210 phy-handle = <ðphy1_sw>;
215 phy-mode = "rgmii"; 211 phy-mode = "rgmii";
216 ti,dual-emac-pvid = <2 212 ti,dual-emac-pvid = <2>;
217 }; 213 };
218 }; 214 };
219 215
220 davinci_mdio_sw: mdio@1000 { 216 davinci_mdio_sw: mdio@1000 {
221 compatible = "ti,cpsw-mdio","t 217 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
222 reg = <0x1000 0x100>; 218 reg = <0x1000 0x100>;
223 clocks = <&gmac_clkctrl DRA7_G 219 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
224 clock-names = "fck"; 220 clock-names = "fck";
225 #address-cells = <1>; 221 #address-cells = <1>;
226 #size-cells = <0>; 222 #size-cells = <0>;
227 bus_freq = <1000000>; 223 bus_freq = <1000000>;
228 224
229 ethphy0_sw: ethernet-phy@0 { 225 ethphy0_sw: ethernet-phy@0 {
230 reg = <0>; 226 reg = <0>;
231 }; 227 };
232 228
233 ethphy1_sw: ethernet-phy@1 { 229 ethphy1_sw: ethernet-phy@1 {
234 reg = <1>; 230 reg = <1>;
235 }; 231 };
236 }; 232 };
237 233
238 cpts { 234 cpts {
239 clocks = <&gmac_clkctrl DRA7_G 235 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
240 clock-names = "cpts"; 236 clock-names = "cpts";
241 }; 237 };
242 }; 238 };
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