1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw 4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: TI SoC Ethernet Switch Controller (CPSW 7 title: TI SoC Ethernet Switch Controller (CPSW)
8 8
9 maintainers: 9 maintainers:
10 - Siddharth Vadapalli <s-vadapalli@ti.com> 10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org> 11 - Roger Quadros <rogerq@kernel.org>
12 12
13 description: 13 description:
14 The 3-port switch gigabit ethernet subsystem 14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an et 15 communication and can be configured as an ethernet switch. It provides the
16 gigabit media independent interface (GMII),r 16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media 17 independent interface (RGMII), reduced media independent interface (RMII),
18 the management data input output (MDIO) for 18 the management data input output (MDIO) for physical layer device (PHY)
19 management. 19 management.
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 oneOf: 23 oneOf:
24 - const: ti,cpsw-switch 24 - const: ti,cpsw-switch
25 - items: 25 - items:
26 - const: ti,am335x-cpsw-switch 26 - const: ti,am335x-cpsw-switch
27 - const: ti,cpsw-switch 27 - const: ti,cpsw-switch
28 - items: 28 - items:
29 - const: ti,am4372-cpsw-switch 29 - const: ti,am4372-cpsw-switch
30 - const: ti,cpsw-switch 30 - const: ti,cpsw-switch
31 - items: 31 - items:
32 - const: ti,dra7-cpsw-switch 32 - const: ti,dra7-cpsw-switch
33 - const: ti,cpsw-switch 33 - const: ti,cpsw-switch
34 34
35 reg: 35 reg:
36 maxItems: 1 36 maxItems: 1
37 description: 37 description:
38 The physical base address and size of fu 38 The physical base address and size of full the CPSW module IO range
39 39
40 '#address-cells': 40 '#address-cells':
41 const: 1 41 const: 1
42 42
43 '#size-cells': 43 '#size-cells':
44 const: 1 44 const: 1
45 45
46 ranges: true 46 ranges: true
47 47
48 clocks: 48 clocks:
49 maxItems: 1 49 maxItems: 1
50 description: CPSW functional clock 50 description: CPSW functional clock
51 51
52 clock-names: 52 clock-names:
53 items: 53 items:
54 - const: fck 54 - const: fck
55 55
56 interrupts: 56 interrupts:
57 items: 57 items:
58 - description: RX_THRESH interrupt 58 - description: RX_THRESH interrupt
59 - description: RX interrupt 59 - description: RX interrupt
60 - description: TX interrupt 60 - description: TX interrupt
61 - description: MISC interrupt 61 - description: MISC interrupt
62 62
63 interrupt-names: 63 interrupt-names:
64 items: 64 items:
65 - const: rx_thresh 65 - const: rx_thresh
66 - const: rx 66 - const: rx
67 - const: tx 67 - const: tx
68 - const: misc 68 - const: misc
69 69
70 pinctrl-names: true 70 pinctrl-names: true
71 71
72 syscon: 72 syscon:
73 $ref: /schemas/types.yaml#/definitions/pha 73 $ref: /schemas/types.yaml#/definitions/phandle
74 description: 74 description:
75 Phandle to the system control device nod 75 Phandle to the system control device node which provides access to
76 efuse IO range with MAC addresses 76 efuse IO range with MAC addresses
77 77
78 ethernet-ports: 78 ethernet-ports:
79 type: object 79 type: object
80 additionalProperties: false 80 additionalProperties: false
81 81
82 properties: 82 properties:
83 '#address-cells': 83 '#address-cells':
84 const: 1 84 const: 1
85 '#size-cells': 85 '#size-cells':
86 const: 0 86 const: 0
87 87
88 patternProperties: 88 patternProperties:
89 "^port@[12]$": 89 "^port@[12]$":
90 type: object 90 type: object
91 description: CPSW external ports 91 description: CPSW external ports
92 92
93 $ref: ethernet-controller.yaml# 93 $ref: ethernet-controller.yaml#
94 unevaluatedProperties: false 94 unevaluatedProperties: false
95 95
96 properties: 96 properties:
97 reg: 97 reg:
98 items: 98 items:
99 - enum: [1, 2] 99 - enum: [1, 2]
100 description: CPSW port number 100 description: CPSW port number
101 101
102 phys: 102 phys:
103 maxItems: 1 103 maxItems: 1
104 description: phandle on phy-gmii-s 104 description: phandle on phy-gmii-sel PHY
105 105
106 label: 106 label:
107 description: label associated with 107 description: label associated with this port
108 108
109 ti,dual-emac-pvid: 109 ti,dual-emac-pvid:
110 $ref: /schemas/types.yaml#/definit 110 $ref: /schemas/types.yaml#/definitions/uint32
111 minimum: 1 111 minimum: 1
112 maximum: 1024 112 maximum: 1024
113 description: 113 description:
114 Specifies default PORT VID to be 114 Specifies default PORT VID to be used to segregate
115 ports. Default value - CPSW port 115 ports. Default value - CPSW port number.
116 116
117 required: 117 required:
118 - reg 118 - reg
119 - phys 119 - phys
120 120
121 cpts: 121 cpts:
122 type: object 122 type: object
123 unevaluatedProperties: false 123 unevaluatedProperties: false
124 description: 124 description:
125 The Common Platform Time Sync (CPTS) mod 125 The Common Platform Time Sync (CPTS) module
126 126
127 properties: 127 properties:
128 clocks: 128 clocks:
129 maxItems: 1 129 maxItems: 1
130 description: CPTS reference clock 130 description: CPTS reference clock
131 131
132 clock-names: 132 clock-names:
133 items: 133 items:
134 - const: cpts 134 - const: cpts
135 135
136 cpts_clock_mult: 136 cpts_clock_mult:
137 $ref: /schemas/types.yaml#/definitions 137 $ref: /schemas/types.yaml#/definitions/uint32
138 description: 138 description:
139 Numerator to convert input clock tic 139 Numerator to convert input clock ticks into ns
140 140
141 cpts_clock_shift: 141 cpts_clock_shift:
142 $ref: /schemas/types.yaml#/definitions 142 $ref: /schemas/types.yaml#/definitions/uint32
143 description: 143 description:
144 Denominator to convert input clock t 144 Denominator to convert input clock ticks into ns.
145 Mult and shift will be calculated ba 145 Mult and shift will be calculated basing on CPTS rftclk frequency if
146 both cpts_clock_shift and cpts_clock 146 both cpts_clock_shift and cpts_clock_mult properties are not provided.
147 147
148 required: 148 required:
149 - clocks 149 - clocks
150 - clock-names 150 - clock-names
151 151
152 patternProperties: 152 patternProperties:
153 "^mdio@": 153 "^mdio@":
154 type: object 154 type: object
155 description: 155 description:
156 CPSW MDIO bus. 156 CPSW MDIO bus.
157 $ref: ti,davinci-mdio.yaml# 157 $ref: ti,davinci-mdio.yaml#
158 158
159 159
160 required: 160 required:
161 - compatible 161 - compatible
162 - reg 162 - reg
163 - ranges 163 - ranges
164 - clocks 164 - clocks
165 - clock-names 165 - clock-names
166 - interrupts 166 - interrupts
167 - interrupt-names 167 - interrupt-names
168 - '#address-cells' 168 - '#address-cells'
169 - '#size-cells' 169 - '#size-cells'
170 170
171 additionalProperties: false 171 additionalProperties: false
172 172
173 examples: 173 examples:
174 - | 174 - |
175 #include <dt-bindings/interrupt-controller 175 #include <dt-bindings/interrupt-controller/irq.h>
176 #include <dt-bindings/interrupt-controller 176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/clock/dra7.h> 177 #include <dt-bindings/clock/dra7.h>
178 178
179 mac_sw: switch@0 { 179 mac_sw: switch@0 {
180 compatible = "ti,dra7-cpsw-switch","ti 180 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
181 reg = <0x0 0x4000>; 181 reg = <0x0 0x4000>;
182 ranges = <0 0 0x4000>; 182 ranges = <0 0 0x4000>;
183 clocks = <&gmac_main_clk>; 183 clocks = <&gmac_main_clk>;
184 clock-names = "fck"; 184 clock-names = "fck";
185 #address-cells = <1>; 185 #address-cells = <1>;
186 #size-cells = <1>; 186 #size-cells = <1>;
187 syscon = <&scm_conf>; 187 syscon = <&scm_conf>;
188 188
189 interrupts = <GIC_SPI 334 IRQ_TYPE_LEV 189 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 335 IRQ_TYPE_LEV 190 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 336 IRQ_TYPE_LEV 191 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 337 IRQ_TYPE_LEV 192 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
193 interrupt-names = "rx_thresh", "rx", " 193 interrupt-names = "rx_thresh", "rx", "tx", "misc";
194 194
195 ethernet-ports { 195 ethernet-ports {
196 #address-cells = <1>; 196 #address-cells = <1>;
197 #size-cells = <0>; 197 #size-cells = <0>;
198 198
199 cpsw_port1: port@1 { 199 cpsw_port1: port@1 {
200 reg = <1>; 200 reg = <1>;
201 label = "port1"; 201 label = "port1";
202 mac-address = [ 00 00 202 mac-address = [ 00 00 00 00 00 00 ];
203 phys = <&phy_gmii_sel 203 phys = <&phy_gmii_sel 1>;
204 phy-handle = <ðphy0 204 phy-handle = <ðphy0_sw>;
205 phy-mode = "rgmii"; 205 phy-mode = "rgmii";
206 ti,dual-emac-pvid = <1 206 ti,dual-emac-pvid = <1>;
207 }; 207 };
208 208
209 cpsw_port2: port@2 { 209 cpsw_port2: port@2 {
210 reg = <2>; 210 reg = <2>;
211 label = "wan"; 211 label = "wan";
212 mac-address = [ 00 00 212 mac-address = [ 00 00 00 00 00 00 ];
213 phys = <&phy_gmii_sel 213 phys = <&phy_gmii_sel 2>;
214 phy-handle = <ðphy1 214 phy-handle = <ðphy1_sw>;
215 phy-mode = "rgmii"; 215 phy-mode = "rgmii";
216 ti,dual-emac-pvid = <2 216 ti,dual-emac-pvid = <2>;
217 }; 217 };
218 }; 218 };
219 219
220 davinci_mdio_sw: mdio@1000 { 220 davinci_mdio_sw: mdio@1000 {
221 compatible = "ti,cpsw-mdio","t 221 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
222 reg = <0x1000 0x100>; 222 reg = <0x1000 0x100>;
223 clocks = <&gmac_clkctrl DRA7_G 223 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
224 clock-names = "fck"; 224 clock-names = "fck";
225 #address-cells = <1>; 225 #address-cells = <1>;
226 #size-cells = <0>; 226 #size-cells = <0>;
227 bus_freq = <1000000>; 227 bus_freq = <1000000>;
228 228
229 ethphy0_sw: ethernet-phy@0 { 229 ethphy0_sw: ethernet-phy@0 {
230 reg = <0>; 230 reg = <0>;
231 }; 231 };
232 232
233 ethphy1_sw: ethernet-phy@1 { 233 ethphy1_sw: ethernet-phy@1 {
234 reg = <1>; 234 reg = <1>;
235 }; 235 };
236 }; 236 };
237 237
238 cpts { 238 cpts {
239 clocks = <&gmac_clkctrl DRA7_G 239 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
240 clock-names = "cpts"; 240 clock-names = "cpts";
241 }; 241 };
242 }; 242 };
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