1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-
2 # Copyright (C) 2019 Texas Instruments Incorpo
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/net/ti,dp83
6 $schema: http://devicetree.org/meta-schemas/co
7
8 title: TI DP83867 ethernet PHY
9
10 allOf:
11 - $ref: ethernet-controller.yaml#
12
13 maintainers:
14 - Andrew Davis <afd@ti.com>
15
16 description: |
17 The DP83867 device is a robust, low power, f
18 transceiver with integrated PMD sublayers to
19 and 1000BASE-T Ethernet protocols.
20
21 The DP83867 is designed for easy implementat
22 LANs. It interfaces directly to twisted pair
23 transformer. This device interfaces directly
24 IEEE 802.3 Standard Media Independent Interf
25 Media Independent Interface (GMII) or Reduce
26
27 Specifications about the Ethernet PHY can be
28 https://www.ti.com/lit/gpn/dp83867ir
29
30 properties:
31 reg:
32 maxItems: 1
33
34 nvmem-cells:
35 maxItems: 1
36 description:
37 Nvmem data cell containing the value to
38 IO_IMPEDANCE_CTRL field of the IO_MUX_CF
39
40 nvmem-cell-names:
41 items:
42 - const: io_impedance_ctrl
43
44 ti,min-output-impedance:
45 type: boolean
46 description: |
47 MAC Interface Impedance control to set
48 to a minimum value (35 ohms).
49
50 ti,max-output-impedance:
51 type: boolean
52 description: |
53 MAC Interface Impedance control to set t
54 to a maximum value (70 ohms).
55 Note: Specifying an io_impedance_ctrl nv
56 ti,min-output-impedance, ti,max-output
57 are mutually exclusive. If more than o
58 cell takes precedence over ti,max-outp
59 turn takes precedence over ti,min-outp
60
61 tx-fifo-depth:
62 $ref: /schemas/types.yaml#/definitions/uin
63 description: |
64 Transmitt FIFO depth see dt-bindings/ne
65
66 rx-fifo-depth:
67 $ref: /schemas/types.yaml#/definitions/uin
68 description: |
69 Receive FIFO depth see dt-bindings/net/
70
71 ti,clk-output-sel:
72 $ref: /schemas/types.yaml#/definitions/uin
73 description: |
74 Muxing option for CLK_OUT pin. See dt-b
75 for applicable values. The CLK_OUT pin c
76 property. When omitted, the PHY's defau
77
78 ti,rx-internal-delay:
79 $ref: /schemas/types.yaml#/definitions/uin
80 description: |
81 RGMII Receive Clock Delay - see dt-bindi
82 for applicable values. Required only if
83 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTER
84
85 ti,tx-internal-delay:
86 $ref: /schemas/types.yaml#/definitions/uin
87 description: |
88 RGMII Transmit Clock Delay - see dt-bind
89 for applicable values. Required only if
90 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTER
91
92 Note: If the interface type is PHY_INT
93 delays will be left at their default
94 strapping. The default strapping wil
95 PHY_INTERFACE_MODE_RGMII, by default
96 internal delay, but as PHY_INTERFACE
97 should use "rgmii-id" if internal de
98 changed in future to cause "rgmii" m
99
100 ti,dp83867-rxctrl-strap-quirk:
101 type: boolean
102 description: |
103 This denotes the fact that the board has
104 mode 1 or 2. To ensure PHY operation, th
105 software needs to take when this pin is
106 See data manual for details.
107
108 ti,sgmii-ref-clock-output-enable:
109 type: boolean
110 description: |
111 This denotes which SGMII configuration i
112 Some MACs work with differential SGMII c
113
114 ti,fifo-depth:
115 deprecated: true
116 $ref: /schemas/types.yaml#/definitions/uin
117 description: |
118 Transmitt FIFO depth- see dt-bindings/ne
119 values.
120
121 required:
122 - reg
123
124 unevaluatedProperties: false
125
126 examples:
127 - |
128 #include <dt-bindings/net/ti-dp83867.h>
129 mdio0 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 ethphy0: ethernet-phy@0 {
133 reg = <0>;
134 tx-fifo-depth = <DP83867_PHYCR_FIFO_DE
135 rx-fifo-depth = <DP83867_PHYCR_FIFO_DE
136 ti,max-output-impedance;
137 ti,clk-output-sel = <DP83867_CLK_O_SEL
138 ti,rx-internal-delay = <DP83867_RGMIID
139 ti,tx-internal-delay = <DP83867_RGMIID
140 };
141 };
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