1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,ax
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: AXI 1G/2.5G Ethernet Subsystem
8
9 description: |
10 Also called AXI 1G/2.5G Ethernet Subsystem,
11 provides connectivity to an external etherne
12 interfaces: MII, GMII, RGMII, SGMII, 1000Bas
13 segments of memory for buffering TX and RX,
14 offloading TX/RX checksum calculation off th
15
16 Management configuration is done through the
17 sent and received through means of an AXI DM
18 includes the DMA driver code, so this driver
19 driver.
20
21 maintainers:
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xi
23
24 properties:
25 compatible:
26 enum:
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
30
31 reg:
32 description:
33 Address and length of the IO space, as w
34 and length of the AXI DMA controller IO
35 axistream-connected is specified, in whi
36 attribute of the node referenced by it i
37 minItems: 1
38 maxItems: 2
39
40 interrupts:
41 items:
42 - description: Ethernet core interrupt
43 - description: Tx DMA interrupt
44 - description: Rx DMA interrupt
45 description:
46 Ethernet core interrupt is optional. If
47 present DMA node should contains TX/RX D
48 resources are mentioned on ethernet node
49 minItems: 1
50
51 phy-handle: true
52
53 xlnx,rxmem:
54 description:
55 Set to allocated memory buffer for Rx/Tx
56 $ref: /schemas/types.yaml#/definitions/uin
57
58 phy-mode:
59 enum:
60 - mii
61 - gmii
62 - rgmii
63 - sgmii
64 - 1000base-x
65
66 xlnx,phy-type:
67 description:
68 Do not use, but still accepted in prefer
69 deprecated: true
70 $ref: /schemas/types.yaml#/definitions/uin
71
72 xlnx,txcsum:
73 description:
74 TX checksum offload. 0 or empty for disa
75 1 to enable partial TX checksum offload
76 checksum offload.
77 $ref: /schemas/types.yaml#/definitions/uin
78 enum: [0, 1, 2]
79
80 xlnx,rxcsum:
81 description:
82 RX checksum offload. 0 or empty for disa
83 1 to enable partial RX checksum offload
84 checksum offload.
85 $ref: /schemas/types.yaml#/definitions/uin
86 enum: [0, 1, 2]
87
88 xlnx,switch-x-sgmii:
89 type: boolean
90 description:
91 Indicate the Ethernet core is configured
92 SGMII modes. If set, the phy-mode should
93 selected on core reset (i.e. by the base
94
95 clocks:
96 items:
97 - description: Clock for AXI register sl
98 - description: AXI4-Stream clock for TXD
99 - description: Ethernet reference clock,
100 and transceivers.
101 - description: MGT reference clock (used
102
103 clock-names:
104 items:
105 - const: s_axi_lite_clk
106 - const: axis_clk
107 - const: ref_clk
108 - const: mgt_clk
109
110 axistream-connected:
111 $ref: /schemas/types.yaml#/definitions/pha
112 description: Phandle of AXI DMA controller
113 used by this device. If this is specifie
114 from that device (DMA registers and DMA
115 this one will be used.
116
117 mdio:
118 type: object
119
120 pcs-handle:
121 description: Phandle to the internal PCS/P
122 modes, where "pcs-handle" should be used
123 and "phy-handle" should point to an exte
124 maxItems: 1
125
126 dmas:
127 minItems: 2
128 maxItems: 32
129 description: TX and RX DMA channel phandle
130
131 dma-names:
132 items:
133 pattern: "^[tr]x_chan([0-9]|1[0-5])$"
134 description:
135 Should be "tx_chan0", "tx_chan1" ... "tx
136 Should be "rx_chan0", "rx_chan1" ... "rx
137 minItems: 2
138 maxItems: 32
139
140 required:
141 - compatible
142 - interrupts
143 - reg
144 - xlnx,rxmem
145 - phy-handle
146
147 allOf:
148 - $ref: /schemas/net/ethernet-controller.yam
149
150 additionalProperties: false
151
152 examples:
153 - |
154 axi_ethernet_eth: ethernet@40c00000 {
155 compatible = "xlnx,axi-ethernet-1.00.a
156 interrupts = <2 0 1>;
157 clock-names = "s_axi_lite_clk", "axis_
158 clocks = <&axi_clk>, <&axi_clk>, <&pl_
159 phy-mode = "mii";
160 reg = <0x40c00000 0x40000>,<0x50c00000
161 dmas = <&xilinx_dma 0>, <&xilinx_dma 1
162 dma-names = "tx_chan0", "rx_chan0";
163 xlnx,rxcsum = <0x2>;
164 xlnx,rxmem = <0x800>;
165 xlnx,txcsum = <0x2>;
166 phy-handle = <&phy0>;
167
168 mdio {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 phy0: ethernet-phy@1 {
172 device_type = "ethernet-phy";
173 reg = <1>;
174 };
175 };
176 };
177
178 - |
179 axi_ethernet_eth1: ethernet@40000000 {
180 compatible = "xlnx,axi-ethernet-1.00.a
181 interrupts = <0>;
182 clock-names = "s_axi_lite_clk", "axis_
183 clocks = <&axi_clk>, <&axi_clk>, <&pl_
184 phy-mode = "mii";
185 reg = <0x40000000 0x40000>;
186 xlnx,rxcsum = <0x2>;
187 xlnx,rxmem = <0x800>;
188 xlnx,txcsum = <0x2>;
189 phy-handle = <&phy1>;
190 axistream-connected = <&dma>;
191
192 mdio {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 phy1: ethernet-phy@1 {
196 device_type = "ethernet-phy";
197 reg = <1>;
198 };
199 };
200 };
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