1 * Nios II Processor Binding 1 * Nios II Processor Binding
2 2
3 This binding specifies what properties availab 3 This binding specifies what properties available in the device tree
4 representation of a Nios II Processor Core. 4 representation of a Nios II Processor Core.
5 5
6 Users can use sopc2dts tool for generating dev 6 Users can use sopc2dts tool for generating device tree sources (dts) from a
7 Qsys system. See more detail in: http://www.al 7 Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
8 8
9 Required properties: 9 Required properties:
10 10
11 - compatible: Compatible property value should 11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index. 12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the nod 13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of ce 14 - #interrupt-cells: Specifies the number of cells needed to encode an
15 interrupt source, should be 1. 15 interrupt source, should be 1.
16 - clock-frequency: Contains the clock frequenc 16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line s 17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line 18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size. 19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size 20 - icache-size: Contains instruction cache size.
21 - altr,pid-num-bits: Specifies the number of b 21 - altr,pid-num-bits: Specifies the number of bits to use to represent the process
22 identifier (PID). 22 identifier (PID).
23 - altr,tlb-num-ways: Specifies the number of s 23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
24 - altr,tlb-num-entries: Specifies the number o 24 - altr,tlb-num-entries: Specifies the number of entries in the TLB.
25 - altr,tlb-ptr-sz: Specifies size of TLB point 25 - altr,tlb-ptr-sz: Specifies size of TLB pointer.
26 - altr,has-mul: Specifies CPU hardware multipl 26 - altr,has-mul: Specifies CPU hardware multiply support, should be 1.
27 - altr,has-mmu: Specifies CPU support MMU supp 27 - altr,has-mmu: Specifies CPU support MMU support, should be 1.
28 - altr,has-initda: Specifies CPU support initd 28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
29 - altr,reset-addr: Specifies CPU reset address 29 - altr,reset-addr: Specifies CPU reset address
30 - altr,fast-tlb-miss-addr: Specifies CPU fast 30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
31 - altr,exception-addr: Specifies CPU exception 31 - altr,exception-addr: Specifies CPU exception address
32 32
33 Optional properties: 33 Optional properties:
34 - altr,has-div: Specifies CPU hardware divide 34 - altr,has-div: Specifies CPU hardware divide support
35 - altr,implementation: Nios II core implementa 35 - altr,implementation: Nios II core implementation, this should be "fast";
36 36
37 Example: 37 Example:
38 38
39 cpu@0 { 39 cpu@0 {
40 device_type = "cpu"; 40 device_type = "cpu";
41 compatible = "altr,nios2-1.0"; 41 compatible = "altr,nios2-1.0";
42 reg = <0>; 42 reg = <0>;
43 interrupt-controller; 43 interrupt-controller;
44 #interrupt-cells = <1>; 44 #interrupt-cells = <1>;
45 clock-frequency = <125000000>; 45 clock-frequency = <125000000>;
46 dcache-line-size = <32>; 46 dcache-line-size = <32>;
47 icache-line-size = <32>; 47 icache-line-size = <32>;
48 dcache-size = <32768>; 48 dcache-size = <32768>;
49 icache-size = <32768>; 49 icache-size = <32768>;
50 altr,implementation = "fast"; 50 altr,implementation = "fast";
51 altr,pid-num-bits = <8>; 51 altr,pid-num-bits = <8>;
52 altr,tlb-num-ways = <16>; 52 altr,tlb-num-ways = <16>;
53 altr,tlb-num-entries = <128>; 53 altr,tlb-num-entries = <128>;
54 altr,tlb-ptr-sz = <7>; 54 altr,tlb-ptr-sz = <7>;
55 altr,has-div = <1>; 55 altr,has-div = <1>;
56 altr,has-mul = <1>; 56 altr,has-mul = <1>;
57 altr,reset-addr = <0xc2800000>; 57 altr,reset-addr = <0xc2800000>;
58 altr,fast-tlb-miss-addr = <0xc7fff400> 58 altr,fast-tlb-miss-addr = <0xc7fff400>;
59 altr,exception-addr = <0xd0000020>; 59 altr,exception-addr = <0xd0000020>;
60 altr,has-initda = <1>; 60 altr,has-initda = <1>;
61 altr,has-mmu = <1>; 61 altr,has-mmu = <1>;
62 }; 62 };
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