1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 %YAML 1.2 2 %YAML 1.2 3 --- 3 --- 4 $id: http://devicetree.org/schemas/nvmem/nvmem 4 $id: http://devicetree.org/schemas/nvmem/nvmem.yaml# 5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 title: NVMEM (Non Volatile Memory) !! 7 title: NVMEM (Non Volatile Memory) Device Tree Bindings 8 8 9 maintainers: 9 maintainers: 10 - Srinivas Kandagatla <srinivas.kandagatla@li 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11 11 12 description: | 12 description: | 13 This binding is intended to represent the lo 13 This binding is intended to represent the location of hardware 14 configuration data stored in NVMEMs like eep 14 configuration data stored in NVMEMs like eeprom, efuses and so on. 15 15 16 On a significant proportion of boards, the m 16 On a significant proportion of boards, the manufacturer has stored 17 some data on NVMEM, for the OS to be able to 17 some data on NVMEM, for the OS to be able to retrieve these 18 information and act upon it. Obviously, the 18 information and act upon it. Obviously, the OS has to know about 19 where to retrieve these data from, and where 19 where to retrieve these data from, and where they are stored on the 20 storage device. 20 storage device. 21 21 22 properties: 22 properties: 23 "#address-cells": 23 "#address-cells": 24 const: 1 24 const: 1 25 25 26 "#size-cells": 26 "#size-cells": 27 const: 1 27 const: 1 28 28 29 read-only: 29 read-only: 30 $ref: /schemas/types.yaml#/definitions/fla 30 $ref: /schemas/types.yaml#/definitions/flag 31 description: 31 description: 32 Mark the provider as read only. 32 Mark the provider as read only. 33 33 34 wp-gpios: 34 wp-gpios: 35 description: 35 description: 36 GPIO to which the write-protect pin of t 36 GPIO to which the write-protect pin of the chip is connected. 37 The write-protect GPIO is asserted, when 37 The write-protect GPIO is asserted, when it's driven high 38 (logical '1') to block the write operati 38 (logical '1') to block the write operation. It's deasserted, 39 when it's driven low (logical '0') to al 39 when it's driven low (logical '0') to allow writing. 40 maxItems: 1 40 maxItems: 1 41 41 42 nvmem-layout: !! 42 patternProperties: 43 $ref: /schemas/nvmem/layouts/nvmem-layout. !! 43 "@[0-9a-f]+(,[0-7])?$": 44 description: !! 44 type: object 45 Alternative to the statically defined nv !! 45 46 container may reference more advanced (d !! 46 properties: 47 parsers. !! 47 reg: >> 48 maxItems: 1 >> 49 description: >> 50 Offset and size in bytes within the storage device. >> 51 >> 52 bits: >> 53 $ref: /schemas/types.yaml#/definitions/uint32-array >> 54 items: >> 55 - minimum: 0 >> 56 maximum: 7 >> 57 description: >> 58 Offset in bit within the address range specified by reg. >> 59 - minimum: 1 >> 60 description: >> 61 Size in bit within the address range specified by reg. >> 62 >> 63 required: >> 64 - reg 48 65 49 additionalProperties: true 66 additionalProperties: true 50 67 51 examples: 68 examples: 52 - | 69 - | 53 #include <dt-bindings/gpio/gpio.h> 70 #include <dt-bindings/gpio/gpio.h> 54 71 55 qfprom: eeprom@700000 { 72 qfprom: eeprom@700000 { 56 compatible = "qcom,msm8974-qfprom", << 57 #address-cells = <1>; 73 #address-cells = <1>; 58 #size-cells = <1>; 74 #size-cells = <1>; 59 reg = <0x00700000 0x100000>; 75 reg = <0x00700000 0x100000>; 60 76 61 wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIG 77 wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 62 78 63 /* ... */ 79 /* ... */ 64 80 65 nvmem-layout { !! 81 /* Data cells */ 66 compatible = "fixed-layout"; !! 82 tsens_calibration: calib@404 { 67 #address-cells = <1>; !! 83 reg = <0x404 0x10>; 68 #size-cells = <1>; !! 84 }; 69 !! 85 70 /* Data cells */ !! 86 tsens_calibration_bckp: calib_bckp@504 { 71 tsens_calibration: calib@404 { !! 87 reg = <0x504 0x11>; 72 reg = <0x404 0x10>; !! 88 bits = <6 128>; 73 }; !! 89 }; 74 !! 90 75 tsens_calibration_bckp: calib_bc !! 91 pvs_version: pvs-version@6 { 76 reg = <0x504 0x11>; !! 92 reg = <0x6 0x2>; 77 bits = <6 128>; !! 93 bits = <7 2>; 78 }; !! 94 }; 79 !! 95 80 pvs_version: pvs-version@6 { !! 96 speed_bin: speed-bin@c{ 81 reg = <0x6 0x2>; !! 97 reg = <0xc 0x1>; 82 bits = <7 2>; !! 98 bits = <2 3>; 83 }; << 84 << 85 speed_bin: speed-bin@c{ << 86 reg = <0xc 0x1>; << 87 bits = <2 3>; << 88 }; << 89 }; 99 }; 90 }; 100 }; 91 101 92 ... 102 ...
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