1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/nvmem/nvmem 4 $id: http://devicetree.org/schemas/nvmem/nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NVMEM (Non Volatile Memory) !! 7 title: NVMEM (Non Volatile Memory) Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Srinivas Kandagatla <srinivas.kandagatla@li 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 11
12 description: | 12 description: |
13 This binding is intended to represent the lo 13 This binding is intended to represent the location of hardware
14 configuration data stored in NVMEMs like eep 14 configuration data stored in NVMEMs like eeprom, efuses and so on.
15 15
16 On a significant proportion of boards, the m 16 On a significant proportion of boards, the manufacturer has stored
17 some data on NVMEM, for the OS to be able to 17 some data on NVMEM, for the OS to be able to retrieve these
18 information and act upon it. Obviously, the 18 information and act upon it. Obviously, the OS has to know about
19 where to retrieve these data from, and where 19 where to retrieve these data from, and where they are stored on the
20 storage device. 20 storage device.
21 21
22 properties: 22 properties:
>> 23 $nodename:
>> 24 pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$"
>> 25
23 "#address-cells": 26 "#address-cells":
24 const: 1 27 const: 1
25 28
26 "#size-cells": 29 "#size-cells":
27 const: 1 30 const: 1
28 31
29 read-only: 32 read-only:
30 $ref: /schemas/types.yaml#/definitions/fla 33 $ref: /schemas/types.yaml#/definitions/flag
31 description: 34 description:
32 Mark the provider as read only. 35 Mark the provider as read only.
33 36
34 wp-gpios: 37 wp-gpios:
35 description: 38 description:
36 GPIO to which the write-protect pin of t 39 GPIO to which the write-protect pin of the chip is connected.
37 The write-protect GPIO is asserted, when 40 The write-protect GPIO is asserted, when it's driven high
38 (logical '1') to block the write operati 41 (logical '1') to block the write operation. It's deasserted,
39 when it's driven low (logical '0') to al 42 when it's driven low (logical '0') to allow writing.
40 maxItems: 1 43 maxItems: 1
41 44
42 nvmem-layout: !! 45 patternProperties:
43 $ref: /schemas/nvmem/layouts/nvmem-layout. !! 46 "^.*@[0-9a-f]+$":
44 description: !! 47 type: object
45 Alternative to the statically defined nv !! 48
46 container may reference more advanced (d !! 49 properties:
47 parsers. !! 50 reg:
>> 51 maxItems: 1
>> 52 description:
>> 53 Offset and size in bytes within the storage device.
>> 54
>> 55 bits:
>> 56 maxItems: 1
>> 57 items:
>> 58 items:
>> 59 - minimum: 0
>> 60 maximum: 7
>> 61 description:
>> 62 Offset in bit within the address range specified by reg.
>> 63 - minimum: 1
>> 64 description:
>> 65 Size in bit within the address range specified by reg.
48 66
49 additionalProperties: true !! 67 required:
>> 68 - reg
50 69
51 examples: 70 examples:
52 - | 71 - |
53 #include <dt-bindings/gpio/gpio.h> 72 #include <dt-bindings/gpio/gpio.h>
54 73
55 qfprom: eeprom@700000 { 74 qfprom: eeprom@700000 {
56 compatible = "qcom,msm8974-qfprom", <<
57 #address-cells = <1>; 75 #address-cells = <1>;
58 #size-cells = <1>; 76 #size-cells = <1>;
59 reg = <0x00700000 0x100000>; 77 reg = <0x00700000 0x100000>;
60 78
61 wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIG 79 wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
62 80
63 /* ... */ 81 /* ... */
64 82
65 nvmem-layout { !! 83 /* Data cells */
66 compatible = "fixed-layout"; !! 84 tsens_calibration: calib@404 {
67 #address-cells = <1>; !! 85 reg = <0x404 0x10>;
68 #size-cells = <1>; !! 86 };
69 !! 87
70 /* Data cells */ !! 88 tsens_calibration_bckp: calib_bckp@504 {
71 tsens_calibration: calib@404 { !! 89 reg = <0x504 0x11>;
72 reg = <0x404 0x10>; !! 90 bits = <6 128>;
73 }; !! 91 };
74 !! 92
75 tsens_calibration_bckp: calib_bc !! 93 pvs_version: pvs-version@6 {
76 reg = <0x504 0x11>; !! 94 reg = <0x6 0x2>;
77 bits = <6 128>; !! 95 bits = <7 2>;
78 }; !! 96 };
79 !! 97
80 pvs_version: pvs-version@6 { !! 98 speed_bin: speed-bin@c{
81 reg = <0x6 0x2>; !! 99 reg = <0xc 0x1>;
82 bits = <7 2>; !! 100 bits = <2 3>;
83 }; <<
84 <<
85 speed_bin: speed-bin@c{ <<
86 reg = <0xc 0x1>; <<
87 bits = <2 3>; <<
88 }; <<
89 }; 101 };
90 }; 102 };
91 103
92 ... 104 ...
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