1 Aardvark PCIe controller 1 Aardvark PCIe controller
2 2
3 This PCIe controller is used on the Marvell Ar 3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
4 4
5 The Device Tree node describing an Aardvark PC 5 The Device Tree node describing an Aardvark PCIe controller must
6 contain the following properties: 6 contain the following properties:
7 7
8 - compatible: Should be "marvell,armada-3700- 8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe contro 9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe 10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3> 11 - #address-cells: set to <3>
12 - #size-cells: set to <2> 12 - #size-cells: set to <2>
13 - device_type: set to "pci" 13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O r 14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1> 15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe con 16 - msi-controller: indicates that the PCIe controller can itself
17 handle MSI interrupts 17 handle MSI interrupts
18 - msi-parent: pointer to the MSI controller t 18 - msi-parent: pointer to the MSI controller to be used
19 - interrupt-map-mask and interrupt-map: stand 19 - interrupt-map-mask and interrupt-map: standard PCI properties to
20 define the mapping of the PCIe interface to 20 define the mapping of the PCIe interface to interrupt numbers.
21 - bus-range: PCI bus numbers covered 21 - bus-range: PCI bus numbers covered
22 - phys: the PCIe PHY handle 22 - phys: the PCIe PHY handle
23 - max-link-speed: see pci.txt 23 - max-link-speed: see pci.txt
24 - reset-gpios: see pci.txt 24 - reset-gpios: see pci.txt
25 25
26 In addition, the Device Tree describing an Aar 26 In addition, the Device Tree describing an Aardvark PCIe controller
27 must include a sub-node that describes the leg 27 must include a sub-node that describes the legacy interrupt controller
28 built into the PCIe controller. This sub-node 28 built into the PCIe controller. This sub-node must have the following
29 properties: 29 properties:
30 30
31 - interrupt-controller 31 - interrupt-controller
32 - #interrupt-cells: set to <1> 32 - #interrupt-cells: set to <1>
33 33
34 Example: 34 Example:
35 35
36 pcie0: pcie@d0070000 { 36 pcie0: pcie@d0070000 {
37 compatible = "marvell,armada-3 37 compatible = "marvell,armada-3700-pcie";
38 device_type = "pci"; 38 device_type = "pci";
39 reg = <0 0xd0070000 0 0x20000> 39 reg = <0 0xd0070000 0 0x20000>;
40 #address-cells = <3>; 40 #address-cells = <3>;
41 #size-cells = <2>; 41 #size-cells = <2>;
42 bus-range = <0x00 0xff>; 42 bus-range = <0x00 0xff>;
43 interrupts = <GIC_SPI 29 IRQ_T 43 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
44 #interrupt-cells = <1>; 44 #interrupt-cells = <1>;
45 msi-controller; 45 msi-controller;
46 msi-parent = <&pcie0>; 46 msi-parent = <&pcie0>;
47 ranges = <0x82000000 0 0xe8000 47 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
48 0x81000000 0 0xe9000 48 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
49 interrupt-map-mask = <0 0 0 7> 49 interrupt-map-mask = <0 0 0 7>;
50 interrupt-map = <0 0 0 1 &pcie 50 interrupt-map = <0 0 0 1 &pcie_intc 0>,
51 <0 0 0 2 &pcie 51 <0 0 0 2 &pcie_intc 1>,
52 <0 0 0 3 &pcie 52 <0 0 0 3 &pcie_intc 2>,
53 <0 0 0 4 &pcie 53 <0 0 0 4 &pcie_intc 3>;
54 phys = <&comphy1 0>; 54 phys = <&comphy1 0>;
55 pcie_intc: interrupt-controlle 55 pcie_intc: interrupt-controller {
56 interrupt-controller; 56 interrupt-controller;
57 #interrupt-cells = <1> 57 #interrupt-cells = <1>;
58 }; 58 };
59 }; 59 };
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