1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pc 4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Cadence PCIe Host 7 title: Cadence PCIe Host
8 8
9 maintainers: 9 maintainers:
10 - Tom Joseph <tjoseph@cadence.com> 10 - Tom Joseph <tjoseph@cadence.com>
11 11
12 allOf: 12 allOf:
13 - $ref: /schemas/pci/pci-host-bridge.yaml# 13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: cdns-pcie.yaml# 14 - $ref: cdns-pcie.yaml#
15 15
16 properties: 16 properties:
17 cdns,max-outbound-regions: 17 cdns,max-outbound-regions:
18 description: maximum number of outbound re 18 description: maximum number of outbound regions
19 $ref: /schemas/types.yaml#/definitions/uin 19 $ref: /schemas/types.yaml#/definitions/uint32
20 minimum: 1 20 minimum: 1
21 maximum: 32 21 maximum: 32
22 default: 32 22 default: 32
23 deprecated: true 23 deprecated: true
24 24
25 cdns,no-bar-match-nbits: 25 cdns,no-bar-match-nbits:
26 description: 26 description:
27 Set into the no BAR match register to co 27 Set into the no BAR match register to configure the number of least
28 significant bits kept during inbound (PC 28 significant bits kept during inbound (PCIe -> AXI) address translations
29 $ref: /schemas/types.yaml#/definitions/uin 29 $ref: /schemas/types.yaml#/definitions/uint32
30 minimum: 0 30 minimum: 0
31 maximum: 64 31 maximum: 64
32 default: 32 32 default: 32
33 deprecated: true 33 deprecated: true
34 34
35 msi-parent: true 35 msi-parent: true
36 36
37 additionalProperties: true 37 additionalProperties: true
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