1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Freescale i.MX6 PCIe host controller
8
9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
12
13 description: |+
14 This PCIe host controller is based on the Sy
15 and thus inherits all the common properties
16 The controller instances are dual mode where
17 Root Port mode or Endpoint mode but one at a
18
19 See fsl,imx6q-pcie-ep.yaml for details on th
20 bindings.
21
22 properties:
23 compatible:
24 enum:
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie
33 - fsl,imx8q-pcie
34
35 clocks:
36 minItems: 3
37 items:
38 - description: PCIe bridge clock.
39 - description: PCIe bus clock.
40 - description: PCIe PHY clock.
41 - description: Additional required clock
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq
43
44 clock-names:
45 minItems: 3
46 maxItems: 4
47
48 interrupts:
49 items:
50 - description: builtin MSI controller.
51
52 interrupt-names:
53 items:
54 - const: msi
55
56 reset-gpio:
57 description: Should specify the GPIO for c
58 reset signal. It's not polarity aware an
59 sequence (L=reset state, H=operation sta
60
61 reset-gpio-active-high:
62 description: If present then the reset seq
63 specified in the "reset-gpio" property i
64 L=operation state) (optional required).
65 type: boolean
66
67 required:
68 - compatible
69 - reg
70 - reg-names
71 - "#address-cells"
72 - "#size-cells"
73 - device_type
74 - bus-range
75 - ranges
76 - interrupts
77 - interrupt-names
78 - "#interrupt-cells"
79 - interrupt-map-mask
80 - interrupt-map
81
82 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y
85 - if:
86 properties:
87 compatible:
88 enum:
89 - fsl,imx6q-pcie
90 - fsl,imx6sx-pcie
91 - fsl,imx6qp-pcie
92 - fsl,imx7d-pcie
93 - fsl,imx8mq-pcie
94 - fsl,imx8mm-pcie
95 - fsl,imx8mp-pcie
96 then:
97 properties:
98 reg:
99 maxItems: 2
100 reg-names:
101 items:
102 - const: dbi
103 - const: config
104
105 - if:
106 properties:
107 compatible:
108 enum:
109 - fsl,imx95-pcie
110 then:
111 properties:
112 reg:
113 minItems: 4
114 maxItems: 4
115 reg-names:
116 items:
117 - const: dbi
118 - const: config
119 - const: atu
120 - const: app
121
122 - if:
123 properties:
124 compatible:
125 enum:
126 - fsl,imx6sx-pcie
127 then:
128 properties:
129 clocks:
130 minItems: 4
131 clock-names:
132 items:
133 - const: pcie
134 - const: pcie_bus
135 - const: pcie_phy
136 - const: pcie_inbound_axi
137
138 - if:
139 properties:
140 compatible:
141 enum:
142 - fsl,imx8mq-pcie
143 - fsl,imx95-pcie
144 then:
145 properties:
146 clocks:
147 minItems: 4
148 clock-names:
149 items:
150 - const: pcie
151 - const: pcie_bus
152 - const: pcie_phy
153 - const: pcie_aux
154
155 - if:
156 properties:
157 compatible:
158 enum:
159 - fsl,imx6q-pcie
160 - fsl,imx6qp-pcie
161 - fsl,imx7d-pcie
162 then:
163 properties:
164 clocks:
165 maxItems: 3
166 clock-names:
167 items:
168 - const: pcie
169 - const: pcie_bus
170 - const: pcie_phy
171
172 - if:
173 properties:
174 compatible:
175 enum:
176 - fsl,imx8mm-pcie
177 - fsl,imx8mp-pcie
178 then:
179 properties:
180 clocks:
181 maxItems: 3
182 clock-names:
183 items:
184 - const: pcie
185 - const: pcie_bus
186 - const: pcie_aux
187
188 - if:
189 properties:
190 compatible:
191 enum:
192 - fsl,imx8q-pcie
193 then:
194 properties:
195 clocks:
196 maxItems: 3
197 clock-names:
198 items:
199 - const: dbi
200 - const: mstr
201 - const: slv
202
203 unevaluatedProperties: false
204
205 examples:
206 - |
207 #include <dt-bindings/clock/imx6qdl-clock.
208 #include <dt-bindings/interrupt-controller
209
210 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config";
215 #address-cells = <3>;
216 #size-cells = <2>;
217 device_type = "pci";
218 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01
220 <0x82000000 0 0x01000000 0x01
221 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV
223 interrupt-names = "msi";
224 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI
227 <0 0 0 2 &gpc GIC_SPI
228 <0 0 0 3 &gpc GIC_SPI
229 <0 0 0 4 &gpc GIC_SPI
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE>
232 <&clks IMX6QDL_CLK_PCIE_REF_12
233 clock-names = "pcie", "pcie_bus", "pci
234 };
235 ...
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