1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where <<
17 Root Port mode or Endpoint mode but one at a <<
18 <<
19 See fsl,imx6q-pcie-ep.yaml for details on th <<
20 bindings. <<
21 16
22 properties: 17 properties:
23 compatible: 18 compatible:
24 enum: 19 enum:
25 - fsl,imx6q-pcie 20 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 21 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 22 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 23 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 24 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie !! 25
31 - fsl,imx8mp-pcie !! 26 reg:
32 - fsl,imx95-pcie !! 27 items:
33 - fsl,imx8q-pcie !! 28 - description: Data Bus Interface (DBI) registers.
>> 29 - description: PCIe configuration space region.
>> 30
>> 31 reg-names:
>> 32 items:
>> 33 - const: dbi
>> 34 - const: config
>> 35
>> 36 interrupts:
>> 37 items:
>> 38 - description: builtin MSI controller.
>> 39
>> 40 interrupt-names:
>> 41 items:
>> 42 - const: msi
34 43
35 clocks: 44 clocks:
36 minItems: 3 45 minItems: 3
37 items: 46 items:
38 - description: PCIe bridge clock. 47 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 48 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 49 - description: PCIe PHY clock.
41 - description: Additional required clock 50 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq !! 51 imx8mq-pcie.
43 52
44 clock-names: 53 clock-names:
45 minItems: 3 54 minItems: 3
46 maxItems: 4 !! 55 items:
>> 56 - const: pcie
>> 57 - const: pcie_bus
>> 58 - const: pcie_phy
>> 59 - enum: [ pcie_inbound_axi, pcie_aux ]
>> 60
>> 61 num-lanes:
>> 62 const: 1
>> 63
>> 64 fsl,imx7d-pcie-phy:
>> 65 $ref: /schemas/types.yaml#/definitions/phandle
>> 66 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
>> 67 required properties for imx7d-pcie and imx8mq-pcie.
47 68
48 interrupts: !! 69 power-domains:
49 items: 70 items:
50 - description: builtin MSI controller. !! 71 - description: The phandle pointing to the DISPLAY domain for
>> 72 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
>> 73 imx8mq-pcie.
>> 74 - description: The phandle pointing to the PCIE_PHY power domains
>> 75 for imx6sx-pcie.
51 76
52 interrupt-names: !! 77 power-domain-names:
53 items: 78 items:
54 - const: msi !! 79 - const: pcie
>> 80 - const: pcie_phy
>> 81
>> 82 resets:
>> 83 maxItems: 3
>> 84 description: Phandles to PCIe-related reset lines exposed by SRC
>> 85 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>> 86
>> 87 reset-names:
>> 88 items:
>> 89 - const: pciephy
>> 90 - const: apps
>> 91 - const: turnoff
>> 92
>> 93 fsl,tx-deemph-gen1:
>> 94 description: Gen1 De-emphasis value (optional required).
>> 95 $ref: /schemas/types.yaml#/definitions/uint32
>> 96 default: 0
>> 97
>> 98 fsl,tx-deemph-gen2-3p5db:
>> 99 description: Gen2 (3.5db) De-emphasis value (optional required).
>> 100 $ref: /schemas/types.yaml#/definitions/uint32
>> 101 default: 0
>> 102
>> 103 fsl,tx-deemph-gen2-6db:
>> 104 description: Gen2 (6db) De-emphasis value (optional required).
>> 105 $ref: /schemas/types.yaml#/definitions/uint32
>> 106 default: 20
>> 107
>> 108 fsl,tx-swing-full:
>> 109 description: Gen2 TX SWING FULL value (optional required).
>> 110 $ref: /schemas/types.yaml#/definitions/uint32
>> 111 default: 127
>> 112
>> 113 fsl,tx-swing-low:
>> 114 description: TX launch amplitude swing_low value (optional required).
>> 115 $ref: /schemas/types.yaml#/definitions/uint32
>> 116 default: 127
>> 117
>> 118 fsl,max-link-speed:
>> 119 description: Specify PCI Gen for link capability (optional required).
>> 120 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
>> 121 requirements and thus for gen2 capability a gen2 compliant clock
>> 122 generator should be used and configured.
>> 123 $ref: /schemas/types.yaml#/definitions/uint32
>> 124 enum: [1, 2, 3, 4]
>> 125 default: 1
55 126
56 reset-gpio: 127 reset-gpio:
57 description: Should specify the GPIO for c 128 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 129 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 130 sequence (L=reset state, H=operation state) (optional required).
60 131
61 reset-gpio-active-high: 132 reset-gpio-active-high:
62 description: If present then the reset seq 133 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 134 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 135 L=operation state) (optional required).
65 type: boolean !! 136
>> 137 vpcie-supply:
>> 138 description: Should specify the regulator in charge of PCIe port power.
>> 139 The regulator will be enabled when initializing the PCIe host and
>> 140 disabled either as part of the init process or when shutting down
>> 141 the host (optional required).
>> 142
>> 143 vph-supply:
>> 144 description: Should specify the regulator in charge of VPH one of
>> 145 the three PCIe PHY powers. This regulator can be supplied by both
>> 146 1.8v and 3.3v voltage supplies (optional required).
66 147
67 required: 148 required:
68 - compatible 149 - compatible
69 - reg 150 - reg
70 - reg-names 151 - reg-names
71 - "#address-cells" 152 - "#address-cells"
72 - "#size-cells" 153 - "#size-cells"
73 - device_type 154 - device_type
74 - bus-range 155 - bus-range
75 - ranges 156 - ranges
>> 157 - num-lanes
76 - interrupts 158 - interrupts
77 - interrupt-names 159 - interrupt-names
78 - "#interrupt-cells" 160 - "#interrupt-cells"
79 - interrupt-map-mask 161 - interrupt-map-mask
80 - interrupt-map 162 - interrupt-map
>> 163 - clocks
>> 164 - clock-names
81 165
82 allOf: 166 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# 167 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y <<
85 - if: <<
86 properties: <<
87 compatible: <<
88 enum: <<
89 - fsl,imx6q-pcie <<
90 - fsl,imx6sx-pcie <<
91 - fsl,imx6qp-pcie <<
92 - fsl,imx7d-pcie <<
93 - fsl,imx8mq-pcie <<
94 - fsl,imx8mm-pcie <<
95 - fsl,imx8mp-pcie <<
96 then: <<
97 properties: <<
98 reg: <<
99 maxItems: 2 <<
100 reg-names: <<
101 items: <<
102 - const: dbi <<
103 - const: config <<
104 <<
105 - if: 168 - if:
106 properties: 169 properties:
107 compatible: 170 compatible:
108 enum: !! 171 contains:
109 - fsl,imx95-pcie !! 172 const: fsl,imx6sx-pcie
110 then: 173 then:
111 properties: 174 properties:
112 reg: <<
113 minItems: 4 <<
114 maxItems: 4 <<
115 reg-names: <<
116 items: <<
117 - const: dbi <<
118 - const: config <<
119 - const: atu <<
120 - const: app <<
121 <<
122 - if: <<
123 properties: <<
124 compatible: <<
125 enum: <<
126 - fsl,imx6sx-pcie <<
127 then: <<
128 properties: <<
129 clocks: <<
130 minItems: 4 <<
131 clock-names: 175 clock-names:
132 items: 176 items:
133 - const: pcie !! 177 - {}
134 - const: pcie_bus !! 178 - {}
135 - const: pcie_phy !! 179 - {}
136 - const: pcie_inbound_axi 180 - const: pcie_inbound_axi
137 <<
138 - if: 181 - if:
139 properties: 182 properties:
140 compatible: 183 compatible:
141 enum: !! 184 contains:
142 - fsl,imx8mq-pcie !! 185 const: fsl,imx8mq-pcie
143 - fsl,imx95-pcie <<
144 then: 186 then:
145 properties: 187 properties:
146 clocks: <<
147 minItems: 4 <<
148 clock-names: 188 clock-names:
149 items: 189 items:
150 - const: pcie !! 190 - {}
151 - const: pcie_bus !! 191 - {}
152 - const: pcie_phy !! 192 - {}
153 - const: pcie_aux 193 - const: pcie_aux
154 <<
155 - if: 194 - if:
156 properties: 195 properties:
157 compatible: 196 compatible:
158 enum: !! 197 not:
159 - fsl,imx6q-pcie !! 198 contains:
160 - fsl,imx6qp-pcie !! 199 enum:
161 - fsl,imx7d-pcie !! 200 - fsl,imx6sx-pcie
>> 201 - fsl,imx8mq-pcie
162 then: 202 then:
163 properties: 203 properties:
164 clocks: <<
165 maxItems: 3 <<
166 clock-names: 204 clock-names:
167 items: <<
168 - const: pcie <<
169 - const: pcie_bus <<
170 - const: pcie_phy <<
171 <<
172 - if: <<
173 properties: <<
174 compatible: <<
175 enum: <<
176 - fsl,imx8mm-pcie <<
177 - fsl,imx8mp-pcie <<
178 then: <<
179 properties: <<
180 clocks: <<
181 maxItems: 3 <<
182 clock-names: <<
183 items: <<
184 - const: pcie <<
185 - const: pcie_bus <<
186 - const: pcie_aux <<
187 <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 enum: <<
192 - fsl,imx8q-pcie <<
193 then: <<
194 properties: <<
195 clocks: <<
196 maxItems: 3 205 maxItems: 3
197 clock-names: <<
198 items: <<
199 - const: dbi <<
200 - const: mstr <<
201 - const: slv <<
202 206
203 unevaluatedProperties: false 207 unevaluatedProperties: false
204 208
205 examples: 209 examples:
206 - | 210 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 211 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 212 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 213
210 pcie: pcie@1ffc000 { 214 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 215 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 216 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 217 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 218 reg-names = "dbi", "config";
215 #address-cells = <3>; 219 #address-cells = <3>;
216 #size-cells = <2>; 220 #size-cells = <2>;
217 device_type = "pci"; 221 device_type = "pci";
218 bus-range = <0x00 0xff>; 222 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 223 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 224 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 225 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 226 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 227 interrupt-names = "msi";
224 #interrupt-cells = <1>; 228 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 229 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 230 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 231 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 232 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 233 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 234 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 235 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 236 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 237 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 238 };
235 ... 239 ...
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