1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where <<
17 Root Port mode or Endpoint mode but one at a <<
18 16
19 See fsl,imx6q-pcie-ep.yaml for details on th !! 17 allOf:
20 bindings. !! 18 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 19
22 properties: 20 properties:
23 compatible: 21 compatible:
24 enum: 22 enum:
25 - fsl,imx6q-pcie 23 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 24 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 25 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 26 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 27 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie !! 28
31 - fsl,imx8mp-pcie !! 29 reg:
32 - fsl,imx95-pcie !! 30 items:
33 - fsl,imx8q-pcie !! 31 - description: Data Bus Interface (DBI) registers.
>> 32 - description: PCIe configuration space region.
>> 33
>> 34 reg-names:
>> 35 items:
>> 36 - const: dbi
>> 37 - const: config
>> 38
>> 39 interrupts:
>> 40 items:
>> 41 - description: builtin MSI controller.
>> 42
>> 43 interrupt-names:
>> 44 items:
>> 45 - const: msi
34 46
35 clocks: 47 clocks:
36 minItems: 3 48 minItems: 3
37 items: 49 items:
38 - description: PCIe bridge clock. 50 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 51 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 52 - description: PCIe PHY clock.
41 - description: Additional required clock 53 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq !! 54 imx8mq-pcie.
43 55
44 clock-names: 56 clock-names:
45 minItems: 3 57 minItems: 3
46 maxItems: 4 !! 58 items:
>> 59 - const: pcie
>> 60 - const: pcie_bus
>> 61 - const: pcie_phy
>> 62 - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
>> 63
>> 64 num-lanes:
>> 65 const: 1
>> 66
>> 67 fsl,imx7d-pcie-phy:
>> 68 $ref: /schemas/types.yaml#/definitions/phandle
>> 69 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
>> 70 required properties for imx7d-pcie and imx8mq-pcie.
47 71
48 interrupts: !! 72 power-domains:
49 items: 73 items:
50 - description: builtin MSI controller. !! 74 - description: The phandle pointing to the DISPLAY domain for
>> 75 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
>> 76 imx8mq-pcie.
>> 77 - description: The phandle pointing to the PCIE_PHY power domains
>> 78 for imx6sx-pcie.
51 79
52 interrupt-names: !! 80 power-domain-names:
53 items: 81 items:
54 - const: msi !! 82 - const: pcie
>> 83 - const: pcie_phy
>> 84
>> 85 resets:
>> 86 maxItems: 3
>> 87 description: Phandles to PCIe-related reset lines exposed by SRC
>> 88 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>> 89
>> 90 reset-names:
>> 91 items:
>> 92 - const: pciephy
>> 93 - const: apps
>> 94 - const: turnoff
>> 95
>> 96 fsl,tx-deemph-gen1:
>> 97 description: Gen1 De-emphasis value (optional required).
>> 98 $ref: /schemas/types.yaml#/definitions/uint32
>> 99 default: 0
>> 100
>> 101 fsl,tx-deemph-gen2-3p5db:
>> 102 description: Gen2 (3.5db) De-emphasis value (optional required).
>> 103 $ref: /schemas/types.yaml#/definitions/uint32
>> 104 default: 0
>> 105
>> 106 fsl,tx-deemph-gen2-6db:
>> 107 description: Gen2 (6db) De-emphasis value (optional required).
>> 108 $ref: /schemas/types.yaml#/definitions/uint32
>> 109 default: 20
>> 110
>> 111 fsl,tx-swing-full:
>> 112 description: Gen2 TX SWING FULL value (optional required).
>> 113 $ref: /schemas/types.yaml#/definitions/uint32
>> 114 default: 127
>> 115
>> 116 fsl,tx-swing-low:
>> 117 description: TX launch amplitude swing_low value (optional required).
>> 118 $ref: /schemas/types.yaml#/definitions/uint32
>> 119 default: 127
>> 120
>> 121 fsl,max-link-speed:
>> 122 description: Specify PCI Gen for link capability (optional required).
>> 123 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
>> 124 requirements and thus for gen2 capability a gen2 compliant clock
>> 125 generator should be used and configured.
>> 126 $ref: /schemas/types.yaml#/definitions/uint32
>> 127 enum: [1, 2, 3, 4]
>> 128 default: 1
>> 129
>> 130 phys:
>> 131 maxItems: 1
>> 132
>> 133 phy-names:
>> 134 const: pcie-phy
55 135
56 reset-gpio: 136 reset-gpio:
57 description: Should specify the GPIO for c 137 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 138 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 139 sequence (L=reset state, H=operation state) (optional required).
60 140
61 reset-gpio-active-high: 141 reset-gpio-active-high:
62 description: If present then the reset seq 142 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 143 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 144 L=operation state) (optional required).
65 type: boolean !! 145
>> 146 vpcie-supply:
>> 147 description: Should specify the regulator in charge of PCIe port power.
>> 148 The regulator will be enabled when initializing the PCIe host and
>> 149 disabled either as part of the init process or when shutting down
>> 150 the host (optional required).
>> 151
>> 152 vph-supply:
>> 153 description: Should specify the regulator in charge of VPH one of
>> 154 the three PCIe PHY powers. This regulator can be supplied by both
>> 155 1.8v and 3.3v voltage supplies (optional required).
66 156
67 required: 157 required:
68 - compatible 158 - compatible
69 - reg 159 - reg
70 - reg-names 160 - reg-names
71 - "#address-cells" 161 - "#address-cells"
72 - "#size-cells" 162 - "#size-cells"
73 - device_type 163 - device_type
74 - bus-range 164 - bus-range
75 - ranges 165 - ranges
>> 166 - num-lanes
76 - interrupts 167 - interrupts
77 - interrupt-names 168 - interrupt-names
78 - "#interrupt-cells" 169 - "#interrupt-cells"
79 - interrupt-map-mask 170 - interrupt-map-mask
80 - interrupt-map 171 - interrupt-map
81 !! 172 - clocks
82 allOf: !! 173 - clock-names
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# <<
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y <<
85 - if: <<
86 properties: <<
87 compatible: <<
88 enum: <<
89 - fsl,imx6q-pcie <<
90 - fsl,imx6sx-pcie <<
91 - fsl,imx6qp-pcie <<
92 - fsl,imx7d-pcie <<
93 - fsl,imx8mq-pcie <<
94 - fsl,imx8mm-pcie <<
95 - fsl,imx8mp-pcie <<
96 then: <<
97 properties: <<
98 reg: <<
99 maxItems: 2 <<
100 reg-names: <<
101 items: <<
102 - const: dbi <<
103 - const: config <<
104 <<
105 - if: <<
106 properties: <<
107 compatible: <<
108 enum: <<
109 - fsl,imx95-pcie <<
110 then: <<
111 properties: <<
112 reg: <<
113 minItems: 4 <<
114 maxItems: 4 <<
115 reg-names: <<
116 items: <<
117 - const: dbi <<
118 - const: config <<
119 - const: atu <<
120 - const: app <<
121 <<
122 - if: <<
123 properties: <<
124 compatible: <<
125 enum: <<
126 - fsl,imx6sx-pcie <<
127 then: <<
128 properties: <<
129 clocks: <<
130 minItems: 4 <<
131 clock-names: <<
132 items: <<
133 - const: pcie <<
134 - const: pcie_bus <<
135 - const: pcie_phy <<
136 - const: pcie_inbound_axi <<
137 <<
138 - if: <<
139 properties: <<
140 compatible: <<
141 enum: <<
142 - fsl,imx8mq-pcie <<
143 - fsl,imx95-pcie <<
144 then: <<
145 properties: <<
146 clocks: <<
147 minItems: 4 <<
148 clock-names: <<
149 items: <<
150 - const: pcie <<
151 - const: pcie_bus <<
152 - const: pcie_phy <<
153 - const: pcie_aux <<
154 <<
155 - if: <<
156 properties: <<
157 compatible: <<
158 enum: <<
159 - fsl,imx6q-pcie <<
160 - fsl,imx6qp-pcie <<
161 - fsl,imx7d-pcie <<
162 then: <<
163 properties: <<
164 clocks: <<
165 maxItems: 3 <<
166 clock-names: <<
167 items: <<
168 - const: pcie <<
169 - const: pcie_bus <<
170 - const: pcie_phy <<
171 <<
172 - if: <<
173 properties: <<
174 compatible: <<
175 enum: <<
176 - fsl,imx8mm-pcie <<
177 - fsl,imx8mp-pcie <<
178 then: <<
179 properties: <<
180 clocks: <<
181 maxItems: 3 <<
182 clock-names: <<
183 items: <<
184 - const: pcie <<
185 - const: pcie_bus <<
186 - const: pcie_aux <<
187 <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 enum: <<
192 - fsl,imx8q-pcie <<
193 then: <<
194 properties: <<
195 clocks: <<
196 maxItems: 3 <<
197 clock-names: <<
198 items: <<
199 - const: dbi <<
200 - const: mstr <<
201 - const: slv <<
202 174
203 unevaluatedProperties: false 175 unevaluatedProperties: false
204 176
205 examples: 177 examples:
206 - | 178 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 179 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 180 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 181
210 pcie: pcie@1ffc000 { 182 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 183 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 184 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 185 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 186 reg-names = "dbi", "config";
215 #address-cells = <3>; 187 #address-cells = <3>;
216 #size-cells = <2>; 188 #size-cells = <2>;
217 device_type = "pci"; 189 device_type = "pci";
218 bus-range = <0x00 0xff>; 190 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 191 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 192 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 193 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 194 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 195 interrupt-names = "msi";
224 #interrupt-cells = <1>; 196 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 197 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 198 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 199 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 200 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 201 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 202 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 203 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 204 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 205 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 206 };
235 ... 207 ...
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