1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where <<
17 Root Port mode or Endpoint mode but one at a <<
18 <<
19 See fsl,imx6q-pcie-ep.yaml for details on th <<
20 bindings. <<
21 16
22 properties: 17 properties:
23 compatible: 18 compatible:
24 enum: 19 enum:
25 - fsl,imx6q-pcie 20 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 21 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 22 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 23 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 24 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie 25 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie 26 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie !! 27
33 - fsl,imx8q-pcie !! 28 reg:
>> 29 items:
>> 30 - description: Data Bus Interface (DBI) registers.
>> 31 - description: PCIe configuration space region.
>> 32
>> 33 reg-names:
>> 34 items:
>> 35 - const: dbi
>> 36 - const: config
>> 37
>> 38 interrupts:
>> 39 items:
>> 40 - description: builtin MSI controller.
>> 41
>> 42 interrupt-names:
>> 43 items:
>> 44 - const: msi
34 45
35 clocks: 46 clocks:
36 minItems: 3 47 minItems: 3
37 items: 48 items:
38 - description: PCIe bridge clock. 49 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 50 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 51 - description: PCIe PHY clock.
41 - description: Additional required clock 52 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq !! 53 imx8mq-pcie.
43 54
44 clock-names: 55 clock-names:
45 minItems: 3 56 minItems: 3
46 maxItems: 4 !! 57 items:
>> 58 - const: pcie
>> 59 - const: pcie_bus
>> 60 - const: pcie_phy
>> 61 - enum: [ pcie_inbound_axi, pcie_aux ]
>> 62
>> 63 num-lanes:
>> 64 const: 1
>> 65
>> 66 fsl,imx7d-pcie-phy:
>> 67 $ref: /schemas/types.yaml#/definitions/phandle
>> 68 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
>> 69 required properties for imx7d-pcie and imx8mq-pcie.
47 70
48 interrupts: !! 71 power-domains:
49 items: 72 items:
50 - description: builtin MSI controller. !! 73 - description: The phandle pointing to the DISPLAY domain for
>> 74 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
>> 75 imx8mq-pcie.
>> 76 - description: The phandle pointing to the PCIE_PHY power domains
>> 77 for imx6sx-pcie.
51 78
52 interrupt-names: !! 79 power-domain-names:
53 items: 80 items:
54 - const: msi !! 81 - const: pcie
>> 82 - const: pcie_phy
>> 83
>> 84 resets:
>> 85 maxItems: 3
>> 86 description: Phandles to PCIe-related reset lines exposed by SRC
>> 87 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>> 88
>> 89 reset-names:
>> 90 items:
>> 91 - const: pciephy
>> 92 - const: apps
>> 93 - const: turnoff
>> 94
>> 95 fsl,tx-deemph-gen1:
>> 96 description: Gen1 De-emphasis value (optional required).
>> 97 $ref: /schemas/types.yaml#/definitions/uint32
>> 98 default: 0
>> 99
>> 100 fsl,tx-deemph-gen2-3p5db:
>> 101 description: Gen2 (3.5db) De-emphasis value (optional required).
>> 102 $ref: /schemas/types.yaml#/definitions/uint32
>> 103 default: 0
>> 104
>> 105 fsl,tx-deemph-gen2-6db:
>> 106 description: Gen2 (6db) De-emphasis value (optional required).
>> 107 $ref: /schemas/types.yaml#/definitions/uint32
>> 108 default: 20
>> 109
>> 110 fsl,tx-swing-full:
>> 111 description: Gen2 TX SWING FULL value (optional required).
>> 112 $ref: /schemas/types.yaml#/definitions/uint32
>> 113 default: 127
>> 114
>> 115 fsl,tx-swing-low:
>> 116 description: TX launch amplitude swing_low value (optional required).
>> 117 $ref: /schemas/types.yaml#/definitions/uint32
>> 118 default: 127
>> 119
>> 120 fsl,max-link-speed:
>> 121 description: Specify PCI Gen for link capability (optional required).
>> 122 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
>> 123 requirements and thus for gen2 capability a gen2 compliant clock
>> 124 generator should be used and configured.
>> 125 $ref: /schemas/types.yaml#/definitions/uint32
>> 126 enum: [1, 2, 3, 4]
>> 127 default: 1
>> 128
>> 129 phys:
>> 130 maxItems: 1
>> 131
>> 132 phy-names:
>> 133 const: pcie-phy
55 134
56 reset-gpio: 135 reset-gpio:
57 description: Should specify the GPIO for c 136 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 137 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 138 sequence (L=reset state, H=operation state) (optional required).
60 139
61 reset-gpio-active-high: 140 reset-gpio-active-high:
62 description: If present then the reset seq 141 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 142 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 143 L=operation state) (optional required).
65 type: boolean 144 type: boolean
66 145
>> 146 vpcie-supply:
>> 147 description: Should specify the regulator in charge of PCIe port power.
>> 148 The regulator will be enabled when initializing the PCIe host and
>> 149 disabled either as part of the init process or when shutting down
>> 150 the host (optional required).
>> 151
>> 152 vph-supply:
>> 153 description: Should specify the regulator in charge of VPH one of
>> 154 the three PCIe PHY powers. This regulator can be supplied by both
>> 155 1.8v and 3.3v voltage supplies (optional required).
>> 156
67 required: 157 required:
68 - compatible 158 - compatible
69 - reg 159 - reg
70 - reg-names 160 - reg-names
71 - "#address-cells" 161 - "#address-cells"
72 - "#size-cells" 162 - "#size-cells"
73 - device_type 163 - device_type
74 - bus-range 164 - bus-range
75 - ranges 165 - ranges
>> 166 - num-lanes
76 - interrupts 167 - interrupts
77 - interrupt-names 168 - interrupt-names
78 - "#interrupt-cells" 169 - "#interrupt-cells"
79 - interrupt-map-mask 170 - interrupt-map-mask
80 - interrupt-map 171 - interrupt-map
>> 172 - clocks
>> 173 - clock-names
81 174
82 allOf: 175 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# 176 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y <<
85 - if: <<
86 properties: <<
87 compatible: <<
88 enum: <<
89 - fsl,imx6q-pcie <<
90 - fsl,imx6sx-pcie <<
91 - fsl,imx6qp-pcie <<
92 - fsl,imx7d-pcie <<
93 - fsl,imx8mq-pcie <<
94 - fsl,imx8mm-pcie <<
95 - fsl,imx8mp-pcie <<
96 then: <<
97 properties: <<
98 reg: <<
99 maxItems: 2 <<
100 reg-names: <<
101 items: <<
102 - const: dbi <<
103 - const: config <<
104 <<
105 - if: <<
106 properties: <<
107 compatible: <<
108 enum: <<
109 - fsl,imx95-pcie <<
110 then: <<
111 properties: <<
112 reg: <<
113 minItems: 4 <<
114 maxItems: 4 <<
115 reg-names: <<
116 items: <<
117 - const: dbi <<
118 - const: config <<
119 - const: atu <<
120 - const: app <<
121 <<
122 - if: 177 - if:
123 properties: 178 properties:
124 compatible: 179 compatible:
125 enum: !! 180 contains:
126 - fsl,imx6sx-pcie !! 181 const: fsl,imx6sx-pcie
127 then: 182 then:
128 properties: 183 properties:
129 clocks: <<
130 minItems: 4 <<
131 clock-names: 184 clock-names:
132 items: 185 items:
133 - const: pcie !! 186 - {}
134 - const: pcie_bus !! 187 - {}
135 - const: pcie_phy !! 188 - {}
136 - const: pcie_inbound_axi 189 - const: pcie_inbound_axi
137 <<
138 - if: 190 - if:
139 properties: 191 properties:
140 compatible: 192 compatible:
141 enum: !! 193 contains:
142 - fsl,imx8mq-pcie !! 194 const: fsl,imx8mq-pcie
143 - fsl,imx95-pcie <<
144 then: 195 then:
145 properties: 196 properties:
146 clocks: <<
147 minItems: 4 <<
148 clock-names: 197 clock-names:
149 items: 198 items:
150 - const: pcie !! 199 - {}
151 - const: pcie_bus !! 200 - {}
152 - const: pcie_phy !! 201 - {}
153 - const: pcie_aux 202 - const: pcie_aux
154 <<
155 - if: <<
156 properties: <<
157 compatible: <<
158 enum: <<
159 - fsl,imx6q-pcie <<
160 - fsl,imx6qp-pcie <<
161 - fsl,imx7d-pcie <<
162 then: <<
163 properties: <<
164 clocks: <<
165 maxItems: 3 <<
166 clock-names: <<
167 items: <<
168 - const: pcie <<
169 - const: pcie_bus <<
170 - const: pcie_phy <<
171 <<
172 - if: 203 - if:
173 properties: 204 properties:
174 compatible: 205 compatible:
175 enum: !! 206 not:
176 - fsl,imx8mm-pcie !! 207 contains:
177 - fsl,imx8mp-pcie !! 208 enum:
>> 209 - fsl,imx6sx-pcie
>> 210 - fsl,imx8mq-pcie
178 then: 211 then:
179 properties: 212 properties:
180 clocks: <<
181 maxItems: 3 <<
182 clock-names: 213 clock-names:
183 items: <<
184 - const: pcie <<
185 - const: pcie_bus <<
186 - const: pcie_aux <<
187 <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 enum: <<
192 - fsl,imx8q-pcie <<
193 then: <<
194 properties: <<
195 clocks: <<
196 maxItems: 3 214 maxItems: 3
197 clock-names: <<
198 items: <<
199 - const: dbi <<
200 - const: mstr <<
201 - const: slv <<
202 215
203 unevaluatedProperties: false 216 unevaluatedProperties: false
204 217
205 examples: 218 examples:
206 - | 219 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 220 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 221 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 222
210 pcie: pcie@1ffc000 { 223 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 224 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 225 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 226 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 227 reg-names = "dbi", "config";
215 #address-cells = <3>; 228 #address-cells = <3>;
216 #size-cells = <2>; 229 #size-cells = <2>;
217 device_type = "pci"; 230 device_type = "pci";
218 bus-range = <0x00 0xff>; 231 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 232 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 233 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 234 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 235 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 236 interrupt-names = "msi";
224 #interrupt-cells = <1>; 237 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 238 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 239 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 240 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 241 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 242 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 243 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 244 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 245 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 246 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 247 };
235 ... 248 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.