1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where <<
17 Root Port mode or Endpoint mode but one at a <<
18 <<
19 See fsl,imx6q-pcie-ep.yaml for details on th <<
20 bindings. <<
21 16
22 properties: 17 properties:
23 compatible: 18 compatible:
24 enum: 19 enum:
25 - fsl,imx6q-pcie 20 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 21 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 22 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 23 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 24 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie 25 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie 26 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie !! 27
33 - fsl,imx8q-pcie !! 28 reg:
>> 29 items:
>> 30 - description: Data Bus Interface (DBI) registers.
>> 31 - description: PCIe configuration space region.
>> 32
>> 33 reg-names:
>> 34 items:
>> 35 - const: dbi
>> 36 - const: config
>> 37
>> 38 interrupts:
>> 39 items:
>> 40 - description: builtin MSI controller.
>> 41
>> 42 interrupt-names:
>> 43 items:
>> 44 - const: msi
34 45
35 clocks: 46 clocks:
36 minItems: 3 47 minItems: 3
37 items: 48 items:
38 - description: PCIe bridge clock. 49 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 50 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 51 - description: PCIe PHY clock.
41 - description: Additional required clock 52 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq !! 53 imx8mq-pcie.
43 54
44 clock-names: 55 clock-names:
45 minItems: 3 56 minItems: 3
46 maxItems: 4 !! 57 items:
>> 58 - const: pcie
>> 59 - const: pcie_bus
>> 60 - enum: [ pcie_phy, pcie_aux ]
>> 61 - enum: [ pcie_inbound_axi, pcie_aux ]
>> 62
>> 63 num-lanes:
>> 64 const: 1
>> 65
>> 66 fsl,imx7d-pcie-phy:
>> 67 $ref: /schemas/types.yaml#/definitions/phandle
>> 68 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
>> 69 required properties for imx7d-pcie and imx8mq-pcie.
47 70
48 interrupts: !! 71 power-domains:
>> 72 minItems: 1
49 items: 73 items:
50 - description: builtin MSI controller. !! 74 - description: The phandle pointing to the DISPLAY domain for
>> 75 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
>> 76 imx8mq-pcie.
>> 77 - description: The phandle pointing to the PCIE_PHY power domains
>> 78 for imx6sx-pcie.
51 79
52 interrupt-names: !! 80 power-domain-names:
>> 81 minItems: 1
53 items: 82 items:
54 - const: msi !! 83 - const: pcie
>> 84 - const: pcie_phy
>> 85
>> 86 resets:
>> 87 minItems: 2
>> 88 maxItems: 3
>> 89 description: Phandles to PCIe-related reset lines exposed by SRC
>> 90 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>> 91
>> 92 reset-names:
>> 93 minItems: 2
>> 94 maxItems: 3
>> 95
>> 96 fsl,tx-deemph-gen1:
>> 97 description: Gen1 De-emphasis value (optional required).
>> 98 $ref: /schemas/types.yaml#/definitions/uint32
>> 99 default: 0
>> 100
>> 101 fsl,tx-deemph-gen2-3p5db:
>> 102 description: Gen2 (3.5db) De-emphasis value (optional required).
>> 103 $ref: /schemas/types.yaml#/definitions/uint32
>> 104 default: 0
>> 105
>> 106 fsl,tx-deemph-gen2-6db:
>> 107 description: Gen2 (6db) De-emphasis value (optional required).
>> 108 $ref: /schemas/types.yaml#/definitions/uint32
>> 109 default: 20
>> 110
>> 111 fsl,tx-swing-full:
>> 112 description: Gen2 TX SWING FULL value (optional required).
>> 113 $ref: /schemas/types.yaml#/definitions/uint32
>> 114 default: 127
>> 115
>> 116 fsl,tx-swing-low:
>> 117 description: TX launch amplitude swing_low value (optional required).
>> 118 $ref: /schemas/types.yaml#/definitions/uint32
>> 119 default: 127
>> 120
>> 121 fsl,max-link-speed:
>> 122 description: Specify PCI Gen for link capability (optional required).
>> 123 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
>> 124 requirements and thus for gen2 capability a gen2 compliant clock
>> 125 generator should be used and configured.
>> 126 $ref: /schemas/types.yaml#/definitions/uint32
>> 127 enum: [1, 2, 3, 4]
>> 128 default: 1
>> 129
>> 130 phys:
>> 131 maxItems: 1
>> 132
>> 133 phy-names:
>> 134 const: pcie-phy
55 135
56 reset-gpio: 136 reset-gpio:
57 description: Should specify the GPIO for c 137 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 138 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 139 sequence (L=reset state, H=operation state) (optional required).
60 140
61 reset-gpio-active-high: 141 reset-gpio-active-high:
62 description: If present then the reset seq 142 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 143 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 144 L=operation state) (optional required).
65 type: boolean 145 type: boolean
66 146
>> 147 vpcie-supply:
>> 148 description: Should specify the regulator in charge of PCIe port power.
>> 149 The regulator will be enabled when initializing the PCIe host and
>> 150 disabled either as part of the init process or when shutting down
>> 151 the host (optional required).
>> 152
>> 153 vph-supply:
>> 154 description: Should specify the regulator in charge of VPH one of
>> 155 the three PCIe PHY powers. This regulator can be supplied by both
>> 156 1.8v and 3.3v voltage supplies (optional required).
>> 157
67 required: 158 required:
68 - compatible 159 - compatible
69 - reg 160 - reg
70 - reg-names 161 - reg-names
71 - "#address-cells" 162 - "#address-cells"
72 - "#size-cells" 163 - "#size-cells"
73 - device_type 164 - device_type
74 - bus-range 165 - bus-range
75 - ranges 166 - ranges
>> 167 - num-lanes
76 - interrupts 168 - interrupts
77 - interrupt-names 169 - interrupt-names
78 - "#interrupt-cells" 170 - "#interrupt-cells"
79 - interrupt-map-mask 171 - interrupt-map-mask
80 - interrupt-map 172 - interrupt-map
>> 173 - clocks
>> 174 - clock-names
81 175
82 allOf: 176 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# 177 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y <<
85 - if: 178 - if:
86 properties: 179 properties:
87 compatible: 180 compatible:
88 enum: !! 181 contains:
89 - fsl,imx6q-pcie !! 182 const: fsl,imx6sx-pcie
90 - fsl,imx6sx-pcie <<
91 - fsl,imx6qp-pcie <<
92 - fsl,imx7d-pcie <<
93 - fsl,imx8mq-pcie <<
94 - fsl,imx8mm-pcie <<
95 - fsl,imx8mp-pcie <<
96 then: 183 then:
97 properties: 184 properties:
98 reg: !! 185 clock-names:
99 maxItems: 2 <<
100 reg-names: <<
101 items: 186 items:
102 - const: dbi !! 187 - {}
103 - const: config !! 188 - {}
104 !! 189 - const: pcie_phy
>> 190 - const: pcie_inbound_axi
>> 191 power-domains:
>> 192 minItems: 2
>> 193 power-domain-names:
>> 194 minItems: 2
105 - if: 195 - if:
106 properties: 196 properties:
107 compatible: 197 compatible:
108 enum: !! 198 contains:
109 - fsl,imx95-pcie !! 199 const: fsl,imx8mq-pcie
110 then: 200 then:
111 properties: 201 properties:
112 reg: !! 202 clock-names:
113 minItems: 4 <<
114 maxItems: 4 <<
115 reg-names: <<
116 items: 203 items:
117 - const: dbi !! 204 - {}
118 - const: config !! 205 - {}
119 - const: atu !! 206 - const: pcie_phy
120 - const: app !! 207 - const: pcie_aux
121 <<
122 - if: 208 - if:
123 properties: 209 properties:
124 compatible: 210 compatible:
125 enum: !! 211 not:
126 - fsl,imx6sx-pcie !! 212 contains:
>> 213 enum:
>> 214 - fsl,imx6sx-pcie
>> 215 - fsl,imx8mq-pcie
127 then: 216 then:
128 properties: 217 properties:
129 clocks: 218 clocks:
130 minItems: 4 !! 219 maxItems: 3
131 clock-names: 220 clock-names:
132 items: !! 221 maxItems: 3
133 - const: pcie <<
134 - const: pcie_bus <<
135 - const: pcie_phy <<
136 - const: pcie_inbound_axi <<
137 222
138 - if: 223 - if:
139 properties: 224 properties:
140 compatible: 225 compatible:
141 enum: !! 226 contains:
142 - fsl,imx8mq-pcie !! 227 enum:
143 - fsl,imx95-pcie !! 228 - fsl,imx6q-pcie
>> 229 - fsl,imx6qp-pcie
>> 230 - fsl,imx7d-pcie
144 then: 231 then:
145 properties: 232 properties:
146 clocks: <<
147 minItems: 4 <<
148 clock-names: 233 clock-names:
149 items: !! 234 maxItems: 3
150 - const: pcie !! 235 contains:
151 - const: pcie_bus !! 236 const: pcie_phy
152 - const: pcie_phy <<
153 - const: pcie_aux <<
154 237
155 - if: 238 - if:
156 properties: 239 properties:
157 compatible: 240 compatible:
158 enum: !! 241 contains:
159 - fsl,imx6q-pcie !! 242 enum:
160 - fsl,imx6qp-pcie !! 243 - fsl,imx8mm-pcie
161 - fsl,imx7d-pcie !! 244 - fsl,imx8mp-pcie
162 then: 245 then:
163 properties: 246 properties:
164 clocks: <<
165 maxItems: 3 <<
166 clock-names: 247 clock-names:
167 items: !! 248 maxItems: 3
168 - const: pcie !! 249 contains:
169 - const: pcie_bus !! 250 const: pcie_aux
170 - const: pcie_phy <<
171 <<
172 - if: 251 - if:
173 properties: 252 properties:
174 compatible: 253 compatible:
175 enum: !! 254 contains:
176 - fsl,imx8mm-pcie !! 255 enum:
177 - fsl,imx8mp-pcie !! 256 - fsl,imx6q-pcie
>> 257 - fsl,imx6qp-pcie
178 then: 258 then:
179 properties: 259 properties:
180 clocks: !! 260 power-domains: false
181 maxItems: 3 !! 261 power-domain-names: false
182 clock-names: !! 262
183 items: !! 263 - if:
184 - const: pcie !! 264 not:
185 - const: pcie_bus !! 265 properties:
186 - const: pcie_aux !! 266 compatible:
>> 267 contains:
>> 268 enum:
>> 269 - fsl,imx6sx-pcie
>> 270 - fsl,imx6q-pcie
>> 271 - fsl,imx6qp-pcie
>> 272 then:
>> 273 properties:
>> 274 power-domains:
>> 275 maxItems: 1
>> 276 power-domain-names: false
187 277
188 - if: 278 - if:
189 properties: 279 properties:
190 compatible: 280 compatible:
191 enum: !! 281 contains:
192 - fsl,imx8q-pcie !! 282 enum:
>> 283 - fsl,imx6q-pcie
>> 284 - fsl,imx6sx-pcie
>> 285 - fsl,imx6qp-pcie
>> 286 - fsl,imx7d-pcie
>> 287 - fsl,imx8mq-pcie
193 then: 288 then:
194 properties: 289 properties:
195 clocks: !! 290 resets:
196 maxItems: 3 !! 291 minItems: 3
197 clock-names: !! 292 reset-names:
>> 293 items:
>> 294 - const: pciephy
>> 295 - const: apps
>> 296 - const: turnoff
>> 297 else:
>> 298 properties:
>> 299 resets:
>> 300 maxItems: 2
>> 301 reset-names:
198 items: 302 items:
199 - const: dbi !! 303 - const: apps
200 - const: mstr !! 304 - const: turnoff
201 - const: slv <<
202 305
203 unevaluatedProperties: false 306 unevaluatedProperties: false
204 307
205 examples: 308 examples:
206 - | 309 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 310 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 311 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 312
210 pcie: pcie@1ffc000 { 313 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 314 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 315 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 316 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 317 reg-names = "dbi", "config";
215 #address-cells = <3>; 318 #address-cells = <3>;
216 #size-cells = <2>; 319 #size-cells = <2>;
217 device_type = "pci"; 320 device_type = "pci";
218 bus-range = <0x00 0xff>; 321 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 322 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 323 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 324 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 325 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 326 interrupt-names = "msi";
224 #interrupt-cells = <1>; 327 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 328 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 329 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 330 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 331 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 332 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 333 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 334 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 335 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 336 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 337 };
235 ... 338 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.