1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where <<
17 Root Port mode or Endpoint mode but one at a <<
18 <<
19 See fsl,imx6q-pcie-ep.yaml for details on th <<
20 bindings. <<
21 16
22 properties: 17 properties:
23 compatible: 18 compatible:
24 enum: 19 enum:
25 - fsl,imx6q-pcie 20 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 21 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 22 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 23 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 24 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie 25 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie 26 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie !! 27 - fsl,imx8mm-pcie-ep
33 - fsl,imx8q-pcie !! 28 - fsl,imx8mq-pcie-ep
>> 29 - fsl,imx8mp-pcie-ep
>> 30
>> 31 reg:
>> 32 items:
>> 33 - description: Data Bus Interface (DBI) registers.
>> 34 - description: PCIe configuration space region.
>> 35
>> 36 reg-names:
>> 37 items:
>> 38 - const: dbi
>> 39 - const: config
>> 40
>> 41 interrupts:
>> 42 items:
>> 43 - description: builtin MSI controller.
>> 44
>> 45 interrupt-names:
>> 46 items:
>> 47 - const: msi
34 48
35 clocks: 49 clocks:
36 minItems: 3 50 minItems: 3
37 items: 51 items:
38 - description: PCIe bridge clock. 52 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 53 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 54 - description: PCIe PHY clock.
41 - description: Additional required clock 55 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq !! 56 imx8mq-pcie.
43 57
44 clock-names: 58 clock-names:
45 minItems: 3 59 minItems: 3
46 maxItems: 4 !! 60 items:
>> 61 - const: pcie
>> 62 - const: pcie_bus
>> 63 - enum: [ pcie_phy, pcie_aux ]
>> 64 - enum: [ pcie_inbound_axi, pcie_aux ]
>> 65
>> 66 num-lanes:
>> 67 const: 1
>> 68
>> 69 fsl,imx7d-pcie-phy:
>> 70 $ref: /schemas/types.yaml#/definitions/phandle
>> 71 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
>> 72 required properties for imx7d-pcie and imx8mq-pcie.
47 73
48 interrupts: !! 74 power-domains:
>> 75 minItems: 1
49 items: 76 items:
50 - description: builtin MSI controller. !! 77 - description: The phandle pointing to the DISPLAY domain for
>> 78 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
>> 79 imx8mq-pcie.
>> 80 - description: The phandle pointing to the PCIE_PHY power domains
>> 81 for imx6sx-pcie.
51 82
52 interrupt-names: !! 83 power-domain-names:
>> 84 minItems: 1
53 items: 85 items:
54 - const: msi !! 86 - const: pcie
>> 87 - const: pcie_phy
>> 88
>> 89 resets:
>> 90 minItems: 2
>> 91 maxItems: 3
>> 92 description: Phandles to PCIe-related reset lines exposed by SRC
>> 93 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
>> 94
>> 95 reset-names:
>> 96 minItems: 2
>> 97 maxItems: 3
>> 98
>> 99 fsl,tx-deemph-gen1:
>> 100 description: Gen1 De-emphasis value (optional required).
>> 101 $ref: /schemas/types.yaml#/definitions/uint32
>> 102 default: 0
>> 103
>> 104 fsl,tx-deemph-gen2-3p5db:
>> 105 description: Gen2 (3.5db) De-emphasis value (optional required).
>> 106 $ref: /schemas/types.yaml#/definitions/uint32
>> 107 default: 0
>> 108
>> 109 fsl,tx-deemph-gen2-6db:
>> 110 description: Gen2 (6db) De-emphasis value (optional required).
>> 111 $ref: /schemas/types.yaml#/definitions/uint32
>> 112 default: 20
>> 113
>> 114 fsl,tx-swing-full:
>> 115 description: Gen2 TX SWING FULL value (optional required).
>> 116 $ref: /schemas/types.yaml#/definitions/uint32
>> 117 default: 127
>> 118
>> 119 fsl,tx-swing-low:
>> 120 description: TX launch amplitude swing_low value (optional required).
>> 121 $ref: /schemas/types.yaml#/definitions/uint32
>> 122 default: 127
>> 123
>> 124 fsl,max-link-speed:
>> 125 description: Specify PCI Gen for link capability (optional required).
>> 126 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
>> 127 requirements and thus for gen2 capability a gen2 compliant clock
>> 128 generator should be used and configured.
>> 129 $ref: /schemas/types.yaml#/definitions/uint32
>> 130 enum: [1, 2, 3, 4]
>> 131 default: 1
>> 132
>> 133 phys:
>> 134 maxItems: 1
>> 135
>> 136 phy-names:
>> 137 const: pcie-phy
55 138
56 reset-gpio: 139 reset-gpio:
57 description: Should specify the GPIO for c 140 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 141 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 142 sequence (L=reset state, H=operation state) (optional required).
60 143
61 reset-gpio-active-high: 144 reset-gpio-active-high:
62 description: If present then the reset seq 145 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 146 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 147 L=operation state) (optional required).
65 type: boolean 148 type: boolean
66 149
>> 150 vpcie-supply:
>> 151 description: Should specify the regulator in charge of PCIe port power.
>> 152 The regulator will be enabled when initializing the PCIe host and
>> 153 disabled either as part of the init process or when shutting down
>> 154 the host (optional required).
>> 155
>> 156 vph-supply:
>> 157 description: Should specify the regulator in charge of VPH one of
>> 158 the three PCIe PHY powers. This regulator can be supplied by both
>> 159 1.8v and 3.3v voltage supplies (optional required).
>> 160
67 required: 161 required:
68 - compatible 162 - compatible
69 - reg 163 - reg
70 - reg-names 164 - reg-names
71 - "#address-cells" 165 - "#address-cells"
72 - "#size-cells" 166 - "#size-cells"
73 - device_type 167 - device_type
74 - bus-range 168 - bus-range
75 - ranges 169 - ranges
>> 170 - num-lanes
76 - interrupts 171 - interrupts
77 - interrupt-names 172 - interrupt-names
78 - "#interrupt-cells" 173 - "#interrupt-cells"
79 - interrupt-map-mask 174 - interrupt-map-mask
80 - interrupt-map 175 - interrupt-map
>> 176 - clocks
>> 177 - clock-names
81 178
82 allOf: 179 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# 180 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y <<
85 - if: 181 - if:
86 properties: 182 properties:
87 compatible: 183 compatible:
88 enum: !! 184 contains:
89 - fsl,imx6q-pcie !! 185 const: fsl,imx6sx-pcie
90 - fsl,imx6sx-pcie <<
91 - fsl,imx6qp-pcie <<
92 - fsl,imx7d-pcie <<
93 - fsl,imx8mq-pcie <<
94 - fsl,imx8mm-pcie <<
95 - fsl,imx8mp-pcie <<
96 then: 186 then:
97 properties: 187 properties:
98 reg: !! 188 clock-names:
99 maxItems: 2 <<
100 reg-names: <<
101 items: 189 items:
102 - const: dbi !! 190 - {}
103 - const: config !! 191 - {}
104 !! 192 - const: pcie_phy
>> 193 - const: pcie_inbound_axi
>> 194 power-domains:
>> 195 minItems: 2
>> 196 power-domain-names:
>> 197 minItems: 2
105 - if: 198 - if:
106 properties: 199 properties:
107 compatible: 200 compatible:
108 enum: !! 201 contains:
109 - fsl,imx95-pcie !! 202 const: fsl,imx8mq-pcie
110 then: 203 then:
111 properties: 204 properties:
112 reg: !! 205 clock-names:
113 minItems: 4 <<
114 maxItems: 4 <<
115 reg-names: <<
116 items: 206 items:
117 - const: dbi !! 207 - {}
118 - const: config !! 208 - {}
119 - const: atu !! 209 - const: pcie_phy
120 - const: app !! 210 - const: pcie_aux
121 <<
122 - if: 211 - if:
123 properties: 212 properties:
124 compatible: 213 compatible:
125 enum: !! 214 not:
126 - fsl,imx6sx-pcie !! 215 contains:
>> 216 enum:
>> 217 - fsl,imx6sx-pcie
>> 218 - fsl,imx8mq-pcie
127 then: 219 then:
128 properties: 220 properties:
129 clocks: 221 clocks:
130 minItems: 4 !! 222 maxItems: 3
131 clock-names: 223 clock-names:
132 items: !! 224 maxItems: 3
133 - const: pcie <<
134 - const: pcie_bus <<
135 - const: pcie_phy <<
136 - const: pcie_inbound_axi <<
137 225
138 - if: 226 - if:
139 properties: 227 properties:
140 compatible: 228 compatible:
141 enum: !! 229 contains:
142 - fsl,imx8mq-pcie !! 230 enum:
143 - fsl,imx95-pcie !! 231 - fsl,imx6q-pcie
>> 232 - fsl,imx6qp-pcie
>> 233 - fsl,imx7d-pcie
144 then: 234 then:
145 properties: 235 properties:
146 clocks: <<
147 minItems: 4 <<
148 clock-names: 236 clock-names:
149 items: !! 237 maxItems: 3
150 - const: pcie !! 238 contains:
151 - const: pcie_bus !! 239 const: pcie_phy
152 - const: pcie_phy <<
153 - const: pcie_aux <<
154 240
155 - if: 241 - if:
156 properties: 242 properties:
157 compatible: 243 compatible:
158 enum: !! 244 contains:
159 - fsl,imx6q-pcie !! 245 enum:
160 - fsl,imx6qp-pcie !! 246 - fsl,imx8mm-pcie
161 - fsl,imx7d-pcie !! 247 - fsl,imx8mp-pcie
162 then: 248 then:
163 properties: 249 properties:
164 clocks: <<
165 maxItems: 3 <<
166 clock-names: 250 clock-names:
167 items: !! 251 maxItems: 3
168 - const: pcie !! 252 contains:
169 - const: pcie_bus !! 253 const: pcie_aux
170 - const: pcie_phy <<
171 <<
172 - if: 254 - if:
173 properties: 255 properties:
174 compatible: 256 compatible:
175 enum: !! 257 contains:
176 - fsl,imx8mm-pcie !! 258 enum:
177 - fsl,imx8mp-pcie !! 259 - fsl,imx6q-pcie
>> 260 - fsl,imx6qp-pcie
178 then: 261 then:
179 properties: 262 properties:
180 clocks: !! 263 power-domains: false
181 maxItems: 3 !! 264 power-domain-names: false
182 clock-names: !! 265
183 items: !! 266 - if:
184 - const: pcie !! 267 not:
185 - const: pcie_bus !! 268 properties:
186 - const: pcie_aux !! 269 compatible:
>> 270 contains:
>> 271 enum:
>> 272 - fsl,imx6sx-pcie
>> 273 - fsl,imx6q-pcie
>> 274 - fsl,imx6qp-pcie
>> 275 then:
>> 276 properties:
>> 277 power-domains:
>> 278 maxItems: 1
>> 279 power-domain-names: false
187 280
188 - if: 281 - if:
189 properties: 282 properties:
190 compatible: 283 compatible:
191 enum: !! 284 contains:
192 - fsl,imx8q-pcie !! 285 enum:
>> 286 - fsl,imx6q-pcie
>> 287 - fsl,imx6sx-pcie
>> 288 - fsl,imx6qp-pcie
>> 289 - fsl,imx7d-pcie
>> 290 - fsl,imx8mq-pcie
193 then: 291 then:
194 properties: 292 properties:
195 clocks: !! 293 resets:
196 maxItems: 3 !! 294 minItems: 3
197 clock-names: !! 295 reset-names:
>> 296 items:
>> 297 - const: pciephy
>> 298 - const: apps
>> 299 - const: turnoff
>> 300 else:
>> 301 properties:
>> 302 resets:
>> 303 maxItems: 2
>> 304 reset-names:
198 items: 305 items:
199 - const: dbi !! 306 - const: apps
200 - const: mstr !! 307 - const: turnoff
201 - const: slv <<
202 308
203 unevaluatedProperties: false 309 unevaluatedProperties: false
204 310
205 examples: 311 examples:
206 - | 312 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 313 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 314 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 315
210 pcie: pcie@1ffc000 { 316 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 317 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 318 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 319 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 320 reg-names = "dbi", "config";
215 #address-cells = <3>; 321 #address-cells = <3>;
216 #size-cells = <2>; 322 #size-cells = <2>;
217 device_type = "pci"; 323 device_type = "pci";
218 bus-range = <0x00 0xff>; 324 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 325 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 326 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 327 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 328 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 329 interrupt-names = "msi";
224 #interrupt-cells = <1>; 330 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 331 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 332 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 333 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 334 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 335 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 336 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 337 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 338 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 339 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 340 };
235 ... 341 ...
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