1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where 16 The controller instances are dual mode where in they can work either in
17 Root Port mode or Endpoint mode but one at a 17 Root Port mode or Endpoint mode but one at a time.
18 18
19 See fsl,imx6q-pcie-ep.yaml for details on th 19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
20 bindings. 20 bindings.
21 21
22 properties: 22 properties:
23 compatible: 23 compatible:
24 enum: 24 enum:
25 - fsl,imx6q-pcie 25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 29 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie 30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie 31 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie !! 32
33 - fsl,imx8q-pcie !! 33 reg:
>> 34 items:
>> 35 - description: Data Bus Interface (DBI) registers.
>> 36 - description: PCIe configuration space region.
>> 37
>> 38 reg-names:
>> 39 items:
>> 40 - const: dbi
>> 41 - const: config
34 42
35 clocks: 43 clocks:
36 minItems: 3 44 minItems: 3
37 items: 45 items:
38 - description: PCIe bridge clock. 46 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 47 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 48 - description: PCIe PHY clock.
41 - description: Additional required clock 49 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq 50 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
43 51
44 clock-names: 52 clock-names:
45 minItems: 3 53 minItems: 3
46 maxItems: 4 54 maxItems: 4
47 55
48 interrupts: 56 interrupts:
49 items: 57 items:
50 - description: builtin MSI controller. 58 - description: builtin MSI controller.
51 59
52 interrupt-names: 60 interrupt-names:
53 items: 61 items:
54 - const: msi 62 - const: msi
55 63
56 reset-gpio: 64 reset-gpio:
57 description: Should specify the GPIO for c 65 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 66 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 67 sequence (L=reset state, H=operation state) (optional required).
60 68
61 reset-gpio-active-high: 69 reset-gpio-active-high:
62 description: If present then the reset seq 70 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 71 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 72 L=operation state) (optional required).
65 type: boolean 73 type: boolean
66 74
67 required: 75 required:
68 - compatible 76 - compatible
69 - reg 77 - reg
70 - reg-names 78 - reg-names
71 - "#address-cells" 79 - "#address-cells"
72 - "#size-cells" 80 - "#size-cells"
73 - device_type 81 - device_type
74 - bus-range 82 - bus-range
75 - ranges 83 - ranges
76 - interrupts 84 - interrupts
77 - interrupt-names 85 - interrupt-names
78 - "#interrupt-cells" 86 - "#interrupt-cells"
79 - interrupt-map-mask 87 - interrupt-map-mask
80 - interrupt-map 88 - interrupt-map
81 89
82 allOf: 90 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# 91 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y 92 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
85 - if: 93 - if:
86 properties: 94 properties:
87 compatible: 95 compatible:
88 enum: 96 enum:
89 - fsl,imx6q-pcie <<
90 - fsl,imx6sx-pcie <<
91 - fsl,imx6qp-pcie <<
92 - fsl,imx7d-pcie <<
93 - fsl,imx8mq-pcie <<
94 - fsl,imx8mm-pcie <<
95 - fsl,imx8mp-pcie <<
96 then: <<
97 properties: <<
98 reg: <<
99 maxItems: 2 <<
100 reg-names: <<
101 items: <<
102 - const: dbi <<
103 - const: config <<
104 <<
105 - if: <<
106 properties: <<
107 compatible: <<
108 enum: <<
109 - fsl,imx95-pcie <<
110 then: <<
111 properties: <<
112 reg: <<
113 minItems: 4 <<
114 maxItems: 4 <<
115 reg-names: <<
116 items: <<
117 - const: dbi <<
118 - const: config <<
119 - const: atu <<
120 - const: app <<
121 <<
122 - if: <<
123 properties: <<
124 compatible: <<
125 enum: <<
126 - fsl,imx6sx-pcie 97 - fsl,imx6sx-pcie
127 then: 98 then:
128 properties: 99 properties:
129 clocks: 100 clocks:
130 minItems: 4 101 minItems: 4
131 clock-names: 102 clock-names:
132 items: 103 items:
133 - const: pcie 104 - const: pcie
134 - const: pcie_bus 105 - const: pcie_bus
135 - const: pcie_phy 106 - const: pcie_phy
136 - const: pcie_inbound_axi 107 - const: pcie_inbound_axi
137 108
138 - if: 109 - if:
139 properties: 110 properties:
140 compatible: 111 compatible:
141 enum: 112 enum:
142 - fsl,imx8mq-pcie 113 - fsl,imx8mq-pcie
143 - fsl,imx95-pcie <<
144 then: 114 then:
145 properties: 115 properties:
146 clocks: 116 clocks:
147 minItems: 4 117 minItems: 4
148 clock-names: 118 clock-names:
149 items: 119 items:
150 - const: pcie 120 - const: pcie
151 - const: pcie_bus 121 - const: pcie_bus
152 - const: pcie_phy 122 - const: pcie_phy
153 - const: pcie_aux 123 - const: pcie_aux
154 124
155 - if: 125 - if:
156 properties: 126 properties:
157 compatible: 127 compatible:
158 enum: 128 enum:
159 - fsl,imx6q-pcie 129 - fsl,imx6q-pcie
160 - fsl,imx6qp-pcie 130 - fsl,imx6qp-pcie
161 - fsl,imx7d-pcie 131 - fsl,imx7d-pcie
162 then: 132 then:
163 properties: 133 properties:
164 clocks: 134 clocks:
165 maxItems: 3 135 maxItems: 3
166 clock-names: 136 clock-names:
167 items: 137 items:
168 - const: pcie 138 - const: pcie
169 - const: pcie_bus 139 - const: pcie_bus
170 - const: pcie_phy 140 - const: pcie_phy
171 141
172 - if: 142 - if:
173 properties: 143 properties:
174 compatible: 144 compatible:
175 enum: 145 enum:
176 - fsl,imx8mm-pcie 146 - fsl,imx8mm-pcie
177 - fsl,imx8mp-pcie 147 - fsl,imx8mp-pcie
178 then: 148 then:
179 properties: 149 properties:
180 clocks: 150 clocks:
181 maxItems: 3 151 maxItems: 3
182 clock-names: 152 clock-names:
183 items: 153 items:
184 - const: pcie 154 - const: pcie
185 - const: pcie_bus 155 - const: pcie_bus
186 - const: pcie_aux 156 - const: pcie_aux
187 <<
188 - if: <<
189 properties: <<
190 compatible: <<
191 enum: <<
192 - fsl,imx8q-pcie <<
193 then: <<
194 properties: <<
195 clocks: <<
196 maxItems: 3 <<
197 clock-names: <<
198 items: <<
199 - const: dbi <<
200 - const: mstr <<
201 - const: slv <<
202 157
203 unevaluatedProperties: false 158 unevaluatedProperties: false
204 159
205 examples: 160 examples:
206 - | 161 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 162 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 163 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 164
210 pcie: pcie@1ffc000 { 165 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 166 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 167 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 168 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 169 reg-names = "dbi", "config";
215 #address-cells = <3>; 170 #address-cells = <3>;
216 #size-cells = <2>; 171 #size-cells = <2>;
217 device_type = "pci"; 172 device_type = "pci";
218 bus-range = <0x00 0xff>; 173 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 174 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 175 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 176 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 177 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 178 interrupt-names = "msi";
224 #interrupt-cells = <1>; 179 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 180 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 181 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 182 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 183 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 184 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 185 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 186 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 187 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 188 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 189 };
235 ... 190 ...
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