1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX6 PCIe host controller 7 title: Freescale i.MX6 PCIe host controller
8 8
9 maintainers: 9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de> 10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com> 11 - Richard Zhu <hongxing.zhu@nxp.com>
12 12
13 description: |+ 13 description: |+
14 This PCIe host controller is based on the Sy 14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where 16 The controller instances are dual mode where in they can work either in
17 Root Port mode or Endpoint mode but one at a 17 Root Port mode or Endpoint mode but one at a time.
18 18
19 See fsl,imx6q-pcie-ep.yaml for details on th 19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
20 bindings. 20 bindings.
21 21
22 properties: 22 properties:
23 compatible: 23 compatible:
24 enum: 24 enum:
25 - fsl,imx6q-pcie 25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie 26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie 27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie 28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie 29 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie 30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie 31 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie 32 - fsl,imx95-pcie
33 - fsl,imx8q-pcie 33 - fsl,imx8q-pcie
34 34
35 clocks: 35 clocks:
36 minItems: 3 36 minItems: 3
37 items: 37 items:
38 - description: PCIe bridge clock. 38 - description: PCIe bridge clock.
39 - description: PCIe bus clock. 39 - description: PCIe bus clock.
40 - description: PCIe PHY clock. 40 - description: PCIe PHY clock.
41 - description: Additional required clock 41 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq 42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
43 43
44 clock-names: 44 clock-names:
45 minItems: 3 45 minItems: 3
46 maxItems: 4 46 maxItems: 4
47 47
48 interrupts: 48 interrupts:
49 items: 49 items:
50 - description: builtin MSI controller. 50 - description: builtin MSI controller.
51 51
52 interrupt-names: 52 interrupt-names:
53 items: 53 items:
54 - const: msi 54 - const: msi
55 55
56 reset-gpio: 56 reset-gpio:
57 description: Should specify the GPIO for c 57 description: Should specify the GPIO for controlling the PCI bus device
58 reset signal. It's not polarity aware an 58 reset signal. It's not polarity aware and defaults to active-low reset
59 sequence (L=reset state, H=operation sta 59 sequence (L=reset state, H=operation state) (optional required).
60 60
61 reset-gpio-active-high: 61 reset-gpio-active-high:
62 description: If present then the reset seq 62 description: If present then the reset sequence using the GPIO
63 specified in the "reset-gpio" property i 63 specified in the "reset-gpio" property is reversed (H=reset state,
64 L=operation state) (optional required). 64 L=operation state) (optional required).
65 type: boolean 65 type: boolean
66 66
67 required: 67 required:
68 - compatible 68 - compatible
69 - reg 69 - reg
70 - reg-names 70 - reg-names
71 - "#address-cells" 71 - "#address-cells"
72 - "#size-cells" 72 - "#size-cells"
73 - device_type 73 - device_type
74 - bus-range 74 - bus-range
75 - ranges 75 - ranges
76 - interrupts 76 - interrupts
77 - interrupt-names 77 - interrupt-names
78 - "#interrupt-cells" 78 - "#interrupt-cells"
79 - interrupt-map-mask 79 - interrupt-map-mask
80 - interrupt-map 80 - interrupt-map
81 81
82 allOf: 82 allOf:
83 - $ref: /schemas/pci/snps,dw-pcie.yaml# 83 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.y 84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
85 - if: 85 - if:
86 properties: 86 properties:
87 compatible: 87 compatible:
88 enum: 88 enum:
89 - fsl,imx6q-pcie 89 - fsl,imx6q-pcie
90 - fsl,imx6sx-pcie 90 - fsl,imx6sx-pcie
91 - fsl,imx6qp-pcie 91 - fsl,imx6qp-pcie
92 - fsl,imx7d-pcie 92 - fsl,imx7d-pcie
93 - fsl,imx8mq-pcie 93 - fsl,imx8mq-pcie
94 - fsl,imx8mm-pcie 94 - fsl,imx8mm-pcie
95 - fsl,imx8mp-pcie 95 - fsl,imx8mp-pcie
96 then: 96 then:
97 properties: 97 properties:
98 reg: 98 reg:
99 maxItems: 2 99 maxItems: 2
100 reg-names: 100 reg-names:
101 items: 101 items:
102 - const: dbi 102 - const: dbi
103 - const: config 103 - const: config
104 104
105 - if: 105 - if:
106 properties: 106 properties:
107 compatible: 107 compatible:
108 enum: 108 enum:
109 - fsl,imx95-pcie 109 - fsl,imx95-pcie
110 then: 110 then:
111 properties: 111 properties:
112 reg: 112 reg:
113 minItems: 4 113 minItems: 4
114 maxItems: 4 114 maxItems: 4
115 reg-names: 115 reg-names:
116 items: 116 items:
117 - const: dbi 117 - const: dbi
118 - const: config 118 - const: config
119 - const: atu 119 - const: atu
120 - const: app 120 - const: app
121 121
122 - if: 122 - if:
123 properties: 123 properties:
124 compatible: 124 compatible:
125 enum: 125 enum:
126 - fsl,imx6sx-pcie 126 - fsl,imx6sx-pcie
127 then: 127 then:
128 properties: 128 properties:
129 clocks: 129 clocks:
130 minItems: 4 130 minItems: 4
131 clock-names: 131 clock-names:
132 items: 132 items:
133 - const: pcie 133 - const: pcie
134 - const: pcie_bus 134 - const: pcie_bus
135 - const: pcie_phy 135 - const: pcie_phy
136 - const: pcie_inbound_axi 136 - const: pcie_inbound_axi
137 137
138 - if: 138 - if:
139 properties: 139 properties:
140 compatible: 140 compatible:
141 enum: 141 enum:
142 - fsl,imx8mq-pcie 142 - fsl,imx8mq-pcie
143 - fsl,imx95-pcie 143 - fsl,imx95-pcie
144 then: 144 then:
145 properties: 145 properties:
146 clocks: 146 clocks:
147 minItems: 4 147 minItems: 4
148 clock-names: 148 clock-names:
149 items: 149 items:
150 - const: pcie 150 - const: pcie
151 - const: pcie_bus 151 - const: pcie_bus
152 - const: pcie_phy 152 - const: pcie_phy
153 - const: pcie_aux 153 - const: pcie_aux
154 154
155 - if: 155 - if:
156 properties: 156 properties:
157 compatible: 157 compatible:
158 enum: 158 enum:
159 - fsl,imx6q-pcie 159 - fsl,imx6q-pcie
160 - fsl,imx6qp-pcie 160 - fsl,imx6qp-pcie
161 - fsl,imx7d-pcie 161 - fsl,imx7d-pcie
162 then: 162 then:
163 properties: 163 properties:
164 clocks: 164 clocks:
165 maxItems: 3 165 maxItems: 3
166 clock-names: 166 clock-names:
167 items: 167 items:
168 - const: pcie 168 - const: pcie
169 - const: pcie_bus 169 - const: pcie_bus
170 - const: pcie_phy 170 - const: pcie_phy
171 171
172 - if: 172 - if:
173 properties: 173 properties:
174 compatible: 174 compatible:
175 enum: 175 enum:
176 - fsl,imx8mm-pcie 176 - fsl,imx8mm-pcie
177 - fsl,imx8mp-pcie 177 - fsl,imx8mp-pcie
178 then: 178 then:
179 properties: 179 properties:
180 clocks: 180 clocks:
181 maxItems: 3 181 maxItems: 3
182 clock-names: 182 clock-names:
183 items: 183 items:
184 - const: pcie 184 - const: pcie
185 - const: pcie_bus 185 - const: pcie_bus
186 - const: pcie_aux 186 - const: pcie_aux
187 187
188 - if: 188 - if:
189 properties: 189 properties:
190 compatible: 190 compatible:
191 enum: 191 enum:
192 - fsl,imx8q-pcie 192 - fsl,imx8q-pcie
193 then: 193 then:
194 properties: 194 properties:
195 clocks: 195 clocks:
196 maxItems: 3 196 maxItems: 3
197 clock-names: 197 clock-names:
198 items: 198 items:
199 - const: dbi 199 - const: dbi
200 - const: mstr 200 - const: mstr
201 - const: slv 201 - const: slv
202 202
203 unevaluatedProperties: false 203 unevaluatedProperties: false
204 204
205 examples: 205 examples:
206 - | 206 - |
207 #include <dt-bindings/clock/imx6qdl-clock. 207 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller 208 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 209
210 pcie: pcie@1ffc000 { 210 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie"; 211 compatible = "fsl,imx6q-pcie";
212 reg = <0x01ffc000 0x04000>, 212 reg = <0x01ffc000 0x04000>,
213 <0x01f00000 0x80000>; 213 <0x01f00000 0x80000>;
214 reg-names = "dbi", "config"; 214 reg-names = "dbi", "config";
215 #address-cells = <3>; 215 #address-cells = <3>;
216 #size-cells = <2>; 216 #size-cells = <2>;
217 device_type = "pci"; 217 device_type = "pci";
218 bus-range = <0x00 0xff>; 218 bus-range = <0x00 0xff>;
219 ranges = <0x81000000 0 0 0x01 219 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
220 <0x82000000 0 0x01000000 0x01 220 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
221 num-lanes = <1>; 221 num-lanes = <1>;
222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEV 222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "msi"; 223 interrupt-names = "msi";
224 #interrupt-cells = <1>; 224 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>; 225 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
227 <0 0 0 2 &gpc GIC_SPI 227 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
228 <0 0 0 3 &gpc GIC_SPI 228 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
229 <0 0 0 4 &gpc GIC_SPI 229 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
231 <&clks IMX6QDL_CLK_LVDS1_GATE> 231 <&clks IMX6QDL_CLK_LVDS1_GATE>,
232 <&clks IMX6QDL_CLK_PCIE_REF_12 232 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
233 clock-names = "pcie", "pcie_bus", "pci 233 clock-names = "pcie", "pcie_bus", "pcie_phy";
234 }; 234 };
235 ... 235 ...
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