1 HiSilicon STB PCIe host bridge DT description 1 HiSilicon STB PCIe host bridge DT description
2 2
3 The HiSilicon STB PCIe host controller is base 3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
4 It shares common functions with the DesignWare 4 It shares common functions with the DesignWare PCIe core driver and inherits
5 common properties defined in 5 common properties defined in
6 Documentation/devicetree/bindings/pci/snps,dw- 6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
7 7
8 Additional properties are described here: 8 Additional properties are described here:
9 9
10 Required properties 10 Required properties
11 - compatible: Should be one of the following s 11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie" 12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config r 13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entrie 14 - reg-names: Must include the following entries:
15 "control": control registers of PCIe control 15 "control": control registers of PCIe controller;
16 "rc-dbi": configuration space of PCIe contro 16 "rc-dbi": configuration space of PCIe controller;
17 "config": configuration transaction space of 17 "config": configuration transaction space of PCIe controller.
18 - bus-range: PCI bus numbers covered. 18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt. 19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries. 20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier 21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
22 property. 22 property.
23 - clock-name: Must include the following entri 23 - clock-name: Must include the following entries:
24 "aux": auxiliary gate clock; 24 "aux": auxiliary gate clock;
25 "pipe": pipe gate clock; 25 "pipe": pipe gate clock;
26 "sys": sys gate clock; 26 "sys": sys gate clock;
27 "bus": bus gate clock. 27 "bus": bus gate clock.
28 - resets: List of phandle and reset specifier 28 - resets: List of phandle and reset specifier pairs as listed in reset-names
29 property. 29 property.
30 - reset-names: Must include the following entr 30 - reset-names: Must include the following entries:
31 "soft": soft reset; 31 "soft": soft reset;
32 "sys": sys reset; 32 "sys": sys reset;
33 "bus": bus reset. 33 "bus": bus reset.
34 34
35 Optional properties: 35 Optional properties:
36 - reset-gpios: The gpio to generate PCIe PERST 36 - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
37 - vpcie-supply: The regulator in charge of PCI 37 - vpcie-supply: The regulator in charge of PCIe port power.
38 - phys: List of phandle and phy mode specifier 38 - phys: List of phandle and phy mode specifier, should be 0.
39 - phy-names: Must be "phy". 39 - phy-names: Must be "phy".
40 40
41 Example: 41 Example:
42 pcie@f9860000 { 42 pcie@f9860000 {
43 compatible = "hisilicon,hi3798 43 compatible = "hisilicon,hi3798cv200-pcie";
44 reg = <0xf9860000 0x1000>, 44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>, 45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>; 46 <0xf2000000 0x01000000>;
47 reg-names = "control", "rc-dbi 47 reg-names = "control", "rc-dbi", "config";
48 #address-cells = <3>; 48 #address-cells = <3>;
49 #size-cells = <2>; 49 #size-cells = <2>;
50 device_type = "pci"; 50 device_type = "pci";
51 bus-range = <0 15>; 51 bus-range = <0 15>;
52 num-lanes = <1>; 52 num-lanes = <1>;
53 ranges=<0x81000000 0 0 0xf4000 53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf300000 54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
55 interrupts = <GIC_SPI 128 IRQ_ 55 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
56 interrupt-names = "msi"; 56 interrupt-names = "msi";
57 #interrupt-cells = <1>; 57 #interrupt-cells = <1>;
58 interrupt-map-mask = <0 0 0 0> 58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic 59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
60 clocks = <&crg PCIE_AUX_CLK>, 60 clocks = <&crg PCIE_AUX_CLK>,
61 <&crg PCIE_PIPE_CLK>, 61 <&crg PCIE_PIPE_CLK>,
62 <&crg PCIE_SYS_CLK>, 62 <&crg PCIE_SYS_CLK>,
63 <&crg PCIE_BUS_CLK>; 63 <&crg PCIE_BUS_CLK>;
64 clock-names = "aux", "pipe", " 64 clock-names = "aux", "pipe", "sys", "bus";
65 resets = <&crg 0x18c 6>, <&crg 65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
66 reset-names = "soft", "sys", " 66 reset-names = "soft", "sys", "bus";
67 phys = <&combphy1 PHY_TYPE_PCI 67 phys = <&combphy1 PHY_TYPE_PCIE>;
68 phy-names = "phy"; 68 phy-names = "phy";
69 }; 69 };
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