1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/intel-g 4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: PCIe RC controller on Intel Gateway SoC 7 title: PCIe RC controller on Intel Gateway SoCs
8 8
9 maintainers: 9 maintainers:
10 - Rahul Tanwar <rtanwar@maxlinear.com> !! 10 - Dilip Kota <eswara.kota@linux.intel.com>
11 11
12 select: 12 select:
13 properties: 13 properties:
14 compatible: 14 compatible:
15 contains: 15 contains:
16 const: intel,lgm-pcie 16 const: intel,lgm-pcie
17 required: 17 required:
18 - compatible 18 - compatible
19 19
20 allOf: <<
21 - $ref: /schemas/pci/snps,dw-pcie.yaml# <<
22 <<
23 properties: 20 properties:
24 compatible: 21 compatible:
25 items: 22 items:
26 - const: intel,lgm-pcie 23 - const: intel,lgm-pcie
27 - const: snps,dw-pcie 24 - const: snps,dw-pcie
28 25
>> 26 device_type:
>> 27 const: pci
>> 28
>> 29 "#address-cells":
>> 30 const: 3
>> 31
>> 32 "#size-cells":
>> 33 const: 2
>> 34
29 reg: 35 reg:
30 items: 36 items:
31 - description: Controller control and st 37 - description: Controller control and status registers.
32 - description: PCIe configuration regist 38 - description: PCIe configuration registers.
33 - description: Controller application re 39 - description: Controller application registers.
34 40
35 reg-names: 41 reg-names:
36 items: 42 items:
37 - const: dbi 43 - const: dbi
38 - const: config 44 - const: config
39 - const: app 45 - const: app
40 46
41 ranges: 47 ranges:
42 maxItems: 1 48 maxItems: 1
43 49
44 resets: 50 resets:
45 maxItems: 1 51 maxItems: 1
46 52
47 clocks: 53 clocks:
48 maxItems: 1 54 maxItems: 1
49 55
50 phys: 56 phys:
51 maxItems: 1 57 maxItems: 1
52 58
53 phy-names: 59 phy-names:
54 const: pcie 60 const: pcie
55 61
56 reset-gpios: 62 reset-gpios:
57 maxItems: 1 63 maxItems: 1
58 64
>> 65 linux,pci-domain: true
>> 66
59 num-lanes: 67 num-lanes:
60 maximum: 2 68 maximum: 2
>> 69 description: Number of lanes to use for this port.
>> 70
>> 71 '#interrupt-cells':
>> 72 const: 1
>> 73
>> 74 interrupt-map-mask:
>> 75 description: Standard PCI IRQ mapping properties.
>> 76
>> 77 interrupt-map:
>> 78 description: Standard PCI IRQ mapping properties.
61 79
62 max-link-speed: 80 max-link-speed:
>> 81 description: Specify PCI Gen for link capability.
>> 82 $ref: /schemas/types.yaml#/definitions/uint32
63 enum: [1, 2, 3, 4] 83 enum: [1, 2, 3, 4]
64 default: 1 84 default: 1
65 85
>> 86 bus-range:
>> 87 description: Range of bus numbers associated with this controller.
>> 88
66 reset-assert-ms: 89 reset-assert-ms:
67 description: | 90 description: |
68 Delay after asserting reset to the PCIe 91 Delay after asserting reset to the PCIe device.
69 maximum: 500 92 maximum: 500
70 default: 100 93 default: 100
71 94
72 required: 95 required:
73 - compatible 96 - compatible
>> 97 - device_type
>> 98 - "#address-cells"
>> 99 - "#size-cells"
74 - reg 100 - reg
75 - reg-names 101 - reg-names
76 - ranges 102 - ranges
77 - resets 103 - resets
78 - clocks 104 - clocks
79 - phys 105 - phys
80 - phy-names 106 - phy-names
81 - reset-gpios 107 - reset-gpios
82 - '#interrupt-cells' 108 - '#interrupt-cells'
83 - interrupt-map 109 - interrupt-map
84 - interrupt-map-mask 110 - interrupt-map-mask
85 111
86 unevaluatedProperties: false !! 112 additionalProperties: false
87 113
88 examples: 114 examples:
89 - | 115 - |
90 #include <dt-bindings/gpio/gpio.h> 116 #include <dt-bindings/gpio/gpio.h>
91 pcie10: pcie@d0e00000 { 117 pcie10: pcie@d0e00000 {
92 compatible = "intel,lgm-pcie", "snps,dw- 118 compatible = "intel,lgm-pcie", "snps,dw-pcie";
93 device_type = "pci"; 119 device_type = "pci";
94 #address-cells = <3>; 120 #address-cells = <3>;
95 #size-cells = <2>; 121 #size-cells = <2>;
96 reg = <0xd0e00000 0x1000>, 122 reg = <0xd0e00000 0x1000>,
97 <0xd2000000 0x800000>, 123 <0xd2000000 0x800000>,
98 <0xd0a41000 0x1000>; 124 <0xd0a41000 0x1000>;
99 reg-names = "dbi", "config", "app"; 125 reg-names = "dbi", "config", "app";
100 linux,pci-domain = <0>; 126 linux,pci-domain = <0>;
101 max-link-speed = <4>; 127 max-link-speed = <4>;
102 bus-range = <0x00 0x08>; 128 bus-range = <0x00 0x08>;
103 #interrupt-cells = <1>; 129 #interrupt-cells = <1>;
104 interrupt-map-mask = <0 0 0 0x7>; 130 interrupt-map-mask = <0 0 0 0x7>;
105 interrupt-map = <0 0 0 1 &ioapic1 27 1>, 131 interrupt-map = <0 0 0 1 &ioapic1 27 1>,
106 <0 0 0 2 &ioapic1 28 1>, 132 <0 0 0 2 &ioapic1 28 1>,
107 <0 0 0 3 &ioapic1 29 1>, 133 <0 0 0 3 &ioapic1 29 1>,
108 <0 0 0 4 &ioapic1 30 1>; 134 <0 0 0 4 &ioapic1 30 1>;
109 ranges = <0x02000000 0 0xd4000000 0xd400 135 ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
110 resets = <&rcu0 0x50 0>; 136 resets = <&rcu0 0x50 0>;
111 clocks = <&cgu0 120>; 137 clocks = <&cgu0 120>;
112 phys = <&cb0phy0>; 138 phys = <&cb0phy0>;
113 phy-names = "pcie"; 139 phy-names = "pcie";
114 reset-assert-ms = <500>; 140 reset-assert-ms = <500>;
115 reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW> 141 reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
116 num-lanes = <2>; 142 num-lanes = <2>;
117 }; 143 };
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