1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/intel-g 4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: PCIe RC controller on Intel Gateway SoC 7 title: PCIe RC controller on Intel Gateway SoCs
8 8
9 maintainers: 9 maintainers:
10 - Rahul Tanwar <rtanwar@maxlinear.com> !! 10 - Dilip Kota <eswara.kota@linux.intel.com>
11 <<
12 select: <<
13 properties: <<
14 compatible: <<
15 contains: <<
16 const: intel,lgm-pcie <<
17 required: <<
18 - compatible <<
19 <<
20 allOf: <<
21 - $ref: /schemas/pci/snps,dw-pcie.yaml# <<
22 11
23 properties: 12 properties:
24 compatible: 13 compatible:
25 items: 14 items:
26 - const: intel,lgm-pcie 15 - const: intel,lgm-pcie
27 - const: snps,dw-pcie 16 - const: snps,dw-pcie
28 17
>> 18 device_type:
>> 19 const: pci
>> 20
>> 21 "#address-cells":
>> 22 const: 3
>> 23
>> 24 "#size-cells":
>> 25 const: 2
>> 26
29 reg: 27 reg:
30 items: 28 items:
31 - description: Controller control and st 29 - description: Controller control and status registers.
32 - description: PCIe configuration regist 30 - description: PCIe configuration registers.
33 - description: Controller application re 31 - description: Controller application registers.
34 32
35 reg-names: 33 reg-names:
36 items: 34 items:
37 - const: dbi 35 - const: dbi
38 - const: config 36 - const: config
39 - const: app 37 - const: app
40 38
41 ranges: 39 ranges:
42 maxItems: 1 40 maxItems: 1
43 41
44 resets: 42 resets:
45 maxItems: 1 43 maxItems: 1
46 44
47 clocks: 45 clocks:
48 maxItems: 1 46 maxItems: 1
49 47
50 phys: 48 phys:
51 maxItems: 1 49 maxItems: 1
52 50
53 phy-names: 51 phy-names:
54 const: pcie 52 const: pcie
55 53
56 reset-gpios: 54 reset-gpios:
57 maxItems: 1 55 maxItems: 1
58 56
>> 57 linux,pci-domain: true
>> 58
59 num-lanes: 59 num-lanes:
60 maximum: 2 60 maximum: 2
>> 61 description: Number of lanes to use for this port.
>> 62
>> 63 '#interrupt-cells':
>> 64 const: 1
>> 65
>> 66 interrupt-map-mask:
>> 67 description: Standard PCI IRQ mapping properties.
>> 68
>> 69 interrupt-map:
>> 70 description: Standard PCI IRQ mapping properties.
61 71
62 max-link-speed: 72 max-link-speed:
63 enum: [1, 2, 3, 4] !! 73 description: Specify PCI Gen for link capability.
64 default: 1 !! 74 allOf:
>> 75 - $ref: /schemas/types.yaml#/definitions/uint32
>> 76 - enum: [ 1, 2, 3, 4 ]
>> 77 - default: 1
>> 78
>> 79 bus-range:
>> 80 description: Range of bus numbers associated with this controller.
65 81
66 reset-assert-ms: 82 reset-assert-ms:
67 description: | 83 description: |
68 Delay after asserting reset to the PCIe 84 Delay after asserting reset to the PCIe device.
69 maximum: 500 85 maximum: 500
70 default: 100 86 default: 100
71 87
72 required: 88 required:
73 - compatible 89 - compatible
>> 90 - device_type
>> 91 - "#address-cells"
>> 92 - "#size-cells"
74 - reg 93 - reg
75 - reg-names 94 - reg-names
76 - ranges 95 - ranges
77 - resets 96 - resets
78 - clocks 97 - clocks
79 - phys 98 - phys
80 - phy-names 99 - phy-names
81 - reset-gpios 100 - reset-gpios
82 - '#interrupt-cells' 101 - '#interrupt-cells'
83 - interrupt-map 102 - interrupt-map
84 - interrupt-map-mask 103 - interrupt-map-mask
85 104
86 unevaluatedProperties: false !! 105 additionalProperties: false
87 106
88 examples: 107 examples:
89 - | 108 - |
90 #include <dt-bindings/gpio/gpio.h> 109 #include <dt-bindings/gpio/gpio.h>
91 pcie10: pcie@d0e00000 { 110 pcie10: pcie@d0e00000 {
92 compatible = "intel,lgm-pcie", "snps,dw- 111 compatible = "intel,lgm-pcie", "snps,dw-pcie";
93 device_type = "pci"; 112 device_type = "pci";
94 #address-cells = <3>; 113 #address-cells = <3>;
95 #size-cells = <2>; 114 #size-cells = <2>;
96 reg = <0xd0e00000 0x1000>, 115 reg = <0xd0e00000 0x1000>,
97 <0xd2000000 0x800000>, 116 <0xd2000000 0x800000>,
98 <0xd0a41000 0x1000>; 117 <0xd0a41000 0x1000>;
99 reg-names = "dbi", "config", "app"; 118 reg-names = "dbi", "config", "app";
100 linux,pci-domain = <0>; 119 linux,pci-domain = <0>;
101 max-link-speed = <4>; 120 max-link-speed = <4>;
102 bus-range = <0x00 0x08>; 121 bus-range = <0x00 0x08>;
103 #interrupt-cells = <1>; 122 #interrupt-cells = <1>;
104 interrupt-map-mask = <0 0 0 0x7>; 123 interrupt-map-mask = <0 0 0 0x7>;
105 interrupt-map = <0 0 0 1 &ioapic1 27 1>, 124 interrupt-map = <0 0 0 1 &ioapic1 27 1>,
106 <0 0 0 2 &ioapic1 28 1>, 125 <0 0 0 2 &ioapic1 28 1>,
107 <0 0 0 3 &ioapic1 29 1>, 126 <0 0 0 3 &ioapic1 29 1>,
108 <0 0 0 4 &ioapic1 30 1>; 127 <0 0 0 4 &ioapic1 30 1>;
109 ranges = <0x02000000 0 0xd4000000 0xd400 128 ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
110 resets = <&rcu0 0x50 0>; 129 resets = <&rcu0 0x50 0>;
111 clocks = <&cgu0 120>; 130 clocks = <&cgu0 120>;
112 phys = <&cb0phy0>; 131 phys = <&cb0phy0>;
113 phy-names = "pcie"; 132 phy-names = "pcie";
114 reset-assert-ms = <500>; 133 reset-assert-ms = <500>;
115 reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW> 134 reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
116 num-lanes = <2>; 135 num-lanes = <2>;
117 }; 136 };
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