1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/mediate 4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Gen3 PCIe controller on MediaTek SoCs 7 title: Gen3 PCIe controller on MediaTek SoCs
8 8
9 maintainers: 9 maintainers:
10 - Jianjun Wang <jianjun.wang@mediatek.com> 10 - Jianjun Wang <jianjun.wang@mediatek.com>
11 11
12 description: |+ 12 description: |+
13 PCIe Gen3 MAC controller for MediaTek SoCs, 13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14 and compatible with Gen2, Gen1 speed. 14 and compatible with Gen2, Gen1 speed.
15 15
16 This PCIe controller supports up to 256 MSI 16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17 block diagram is as follows: 17 block diagram is as follows:
18 18
19 +-----+ 19 +-----+
20 | GIC | 20 | GIC |
21 +-----+ 21 +-----+
22 ^ 22 ^
23 | 23 |
24 port->irq 24 port->irq
25 | 25 |
26 +-+-+-+-+-+-+-+-+ 26 +-+-+-+-+-+-+-+-+
27 |0|1|2|3|4|5|6|7| (PCIe intc) 27 |0|1|2|3|4|5|6|7| (PCIe intc)
28 +-+-+-+-+-+-+-+-+ 28 +-+-+-+-+-+-+-+-+
29 ^ ^ ^ 29 ^ ^ ^
30 | | ... | 30 | | ... |
31 +-------+ +------+ +-----------+ 31 +-------+ +------+ +-----------+
32 | | | 32 | | |
33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+- 33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|3 34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+- 35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
36 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 36 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
37 | | | | | | | | | | 37 | | | | | | | | | | | | (MSI vectors)
38 | | | | | | | | | | 38 | | | | | | | | | | | |
39 39
40 (MSI SET0) (MSI SET1) ... (MSI SE 40 (MSI SET0) (MSI SET1) ... (MSI SET7)
41 41
42 With 256 MSI vectors supported, the MSI vect 42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43 each set has its own address for MSI message 43 each set has its own address for MSI message, and supports 32 MSI vectors
44 to generate interrupt. 44 to generate interrupt.
45 45
>> 46 allOf:
>> 47 - $ref: /schemas/pci/pci-bus.yaml#
>> 48
46 properties: 49 properties:
47 compatible: 50 compatible:
48 oneOf: !! 51 const: mediatek,mt8192-pcie
49 - items: <<
50 - enum: <<
51 - mediatek,mt7986-pcie <<
52 - mediatek,mt8188-pcie <<
53 - mediatek,mt8195-pcie <<
54 - const: mediatek,mt8192-pcie <<
55 - const: mediatek,mt8192-pcie <<
56 - const: airoha,en7581-pcie <<
57 52
58 reg: 53 reg:
59 maxItems: 1 54 maxItems: 1
60 55
61 reg-names: 56 reg-names:
62 items: 57 items:
63 - const: pcie-mac 58 - const: pcie-mac
64 59
65 interrupts: 60 interrupts:
66 maxItems: 1 61 maxItems: 1
67 62
68 ranges: 63 ranges:
69 minItems: 1 64 minItems: 1
70 maxItems: 8 65 maxItems: 8
71 66
72 iommu-map: <<
73 maxItems: 1 <<
74 <<
75 iommu-map-mask: <<
76 const: 0 <<
77 <<
78 resets: 67 resets:
79 minItems: 1 68 minItems: 1
80 maxItems: 3 !! 69 maxItems: 2
81 70
82 reset-names: 71 reset-names:
83 minItems: 1 72 minItems: 1
84 maxItems: 3 <<
85 items: 73 items:
86 enum: [ phy, mac, phy-lane0, phy-lane1, !! 74 - const: phy
>> 75 - const: mac
87 76
88 clocks: 77 clocks:
89 minItems: 1 <<
90 maxItems: 6 78 maxItems: 6
91 79
92 clock-names: 80 clock-names:
93 minItems: 1 !! 81 items:
94 maxItems: 6 !! 82 - const: pl_250m
>> 83 - const: tl_26m
>> 84 - const: tl_96m
>> 85 - const: tl_32k
>> 86 - const: peri_26m
>> 87 - const: top_133m
95 88
96 assigned-clocks: 89 assigned-clocks:
97 maxItems: 1 90 maxItems: 1
98 91
99 assigned-clock-parents: 92 assigned-clock-parents:
100 maxItems: 1 93 maxItems: 1
101 94
102 phys: 95 phys:
103 maxItems: 1 96 maxItems: 1
104 97
105 phy-names: 98 phy-names:
106 items: 99 items:
107 - const: pcie-phy 100 - const: pcie-phy
108 101
109 power-domains: <<
110 maxItems: 1 <<
111 <<
112 '#interrupt-cells': 102 '#interrupt-cells':
113 const: 1 103 const: 1
114 104
115 interrupt-controller: 105 interrupt-controller:
116 description: Interrupt controller node for 106 description: Interrupt controller node for handling legacy PCI interrupts.
117 type: object 107 type: object
118 properties: 108 properties:
119 '#address-cells': 109 '#address-cells':
120 const: 0 110 const: 0
121 '#interrupt-cells': 111 '#interrupt-cells':
122 const: 1 112 const: 1
123 interrupt-controller: true 113 interrupt-controller: true
124 114
125 required: 115 required:
126 - '#address-cells' 116 - '#address-cells'
127 - '#interrupt-cells' 117 - '#interrupt-cells'
128 - interrupt-controller 118 - interrupt-controller
129 119
130 additionalProperties: false 120 additionalProperties: false
131 121
132 required: 122 required:
133 - compatible 123 - compatible
134 - reg 124 - reg
135 - reg-names 125 - reg-names
136 - interrupts 126 - interrupts
137 - ranges 127 - ranges
138 - clocks 128 - clocks
139 - clock-names <<
140 - '#interrupt-cells' 129 - '#interrupt-cells'
141 - interrupt-controller 130 - interrupt-controller
142 <<
143 allOf: <<
144 - $ref: /schemas/pci/pci-host-bridge.yaml# <<
145 - if: <<
146 properties: <<
147 compatible: <<
148 const: mediatek,mt8192-pcie <<
149 then: <<
150 properties: <<
151 clocks: <<
152 minItems: 4 <<
153 <<
154 clock-names: <<
155 items: <<
156 - const: pl_250m <<
157 - const: tl_26m <<
158 - const: tl_96m <<
159 - const: tl_32k <<
160 - const: peri_26m <<
161 - const: top_133m <<
162 <<
163 resets: <<
164 minItems: 1 <<
165 maxItems: 2 <<
166 <<
167 reset-names: <<
168 minItems: 1 <<
169 maxItems: 2 <<
170 <<
171 - if: <<
172 properties: <<
173 compatible: <<
174 contains: <<
175 enum: <<
176 - mediatek,mt8188-pcie <<
177 - mediatek,mt8195-pcie <<
178 then: <<
179 properties: <<
180 clocks: <<
181 minItems: 4 <<
182 <<
183 clock-names: <<
184 items: <<
185 - const: pl_250m <<
186 - const: tl_26m <<
187 - const: tl_96m <<
188 - const: tl_32k <<
189 - const: peri_26m <<
190 - const: peri_mem <<
191 <<
192 resets: <<
193 minItems: 1 <<
194 maxItems: 2 <<
195 <<
196 reset-names: <<
197 minItems: 1 <<
198 maxItems: 2 <<
199 <<
200 - if: <<
201 properties: <<
202 compatible: <<
203 contains: <<
204 enum: <<
205 - mediatek,mt7986-pcie <<
206 then: <<
207 properties: <<
208 clocks: <<
209 minItems: 4 <<
210 <<
211 clock-names: <<
212 items: <<
213 - const: pl_250m <<
214 - const: tl_26m <<
215 - const: peri_26m <<
216 - const: top_133m <<
217 <<
218 resets: <<
219 minItems: 1 <<
220 maxItems: 2 <<
221 <<
222 reset-names: <<
223 minItems: 1 <<
224 maxItems: 2 <<
225 <<
226 - if: <<
227 properties: <<
228 compatible: <<
229 const: airoha,en7581-pcie <<
230 then: <<
231 properties: <<
232 clocks: <<
233 maxItems: 1 <<
234 <<
235 clock-names: <<
236 items: <<
237 - const: sys-ck <<
238 <<
239 resets: <<
240 minItems: 3 <<
241 <<
242 reset-names: <<
243 items: <<
244 - const: phy-lane0 <<
245 - const: phy-lane1 <<
246 - const: phy-lane2 <<
247 131
248 unevaluatedProperties: false 132 unevaluatedProperties: false
249 133
250 examples: 134 examples:
251 - | 135 - |
252 #include <dt-bindings/interrupt-controller 136 #include <dt-bindings/interrupt-controller/arm-gic.h>
253 #include <dt-bindings/interrupt-controller 137 #include <dt-bindings/interrupt-controller/irq.h>
254 138
255 bus { 139 bus {
256 #address-cells = <2>; 140 #address-cells = <2>;
257 #size-cells = <2>; 141 #size-cells = <2>;
258 142
259 pcie: pcie@11230000 { 143 pcie: pcie@11230000 {
260 compatible = "mediatek,mt8192-pcie 144 compatible = "mediatek,mt8192-pcie";
261 device_type = "pci"; 145 device_type = "pci";
262 #address-cells = <3>; 146 #address-cells = <3>;
263 #size-cells = <2>; 147 #size-cells = <2>;
264 reg = <0x00 0x11230000 0x00 0x4000 148 reg = <0x00 0x11230000 0x00 0x4000>;
265 reg-names = "pcie-mac"; 149 reg-names = "pcie-mac";
266 interrupts = <GIC_SPI 251 IRQ_TYPE 150 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
267 bus-range = <0x00 0xff>; 151 bus-range = <0x00 0xff>;
268 ranges = <0x82000000 0x00 0x120000 152 ranges = <0x82000000 0x00 0x12000000 0x00
269 0x12000000 0x00 0x100000 153 0x12000000 0x00 0x1000000>;
270 clocks = <&infracfg 44>, 154 clocks = <&infracfg 44>,
271 <&infracfg 40>, 155 <&infracfg 40>,
272 <&infracfg 43>, 156 <&infracfg 43>,
273 <&infracfg 97>, 157 <&infracfg 97>,
274 <&infracfg 99>, 158 <&infracfg 99>,
275 <&infracfg 111>; 159 <&infracfg 111>;
276 clock-names = "pl_250m", "tl_26m", 160 clock-names = "pl_250m", "tl_26m", "tl_96m",
277 "tl_32k", "peri_26m" 161 "tl_32k", "peri_26m", "top_133m";
278 assigned-clocks = <&topckgen 50>; 162 assigned-clocks = <&topckgen 50>;
279 assigned-clock-parents = <&topckge 163 assigned-clock-parents = <&topckgen 91>;
280 164
281 phys = <&pciephy>; 165 phys = <&pciephy>;
282 phy-names = "pcie-phy"; 166 phy-names = "pcie-phy";
283 167
284 resets = <&infracfg_rst 2>, 168 resets = <&infracfg_rst 2>,
285 <&infracfg_rst 3>; 169 <&infracfg_rst 3>;
286 reset-names = "phy", "mac"; 170 reset-names = "phy", "mac";
287 171
288 #interrupt-cells = <1>; 172 #interrupt-cells = <1>;
289 interrupt-map-mask = <0 0 0 0x7>; 173 interrupt-map-mask = <0 0 0 0x7>;
290 interrupt-map = <0 0 0 1 &pcie_int 174 interrupt-map = <0 0 0 1 &pcie_intc 0>,
291 <0 0 0 2 &pcie_int 175 <0 0 0 2 &pcie_intc 1>,
292 <0 0 0 3 &pcie_int 176 <0 0 0 3 &pcie_intc 2>,
293 <0 0 0 4 &pcie_int 177 <0 0 0 4 &pcie_intc 3>;
294 pcie_intc: interrupt-controller { 178 pcie_intc: interrupt-controller {
295 #address-cells = <0>; 179 #address-cells = <0>;
296 #interrupt-cells = <1>; 180 #interrupt-cells = <1>;
297 interrupt-controller; 181 interrupt-controller;
298 }; 182 };
299 }; 183 };
300 }; 184 };
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