1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/rockchi 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: DesignWare based PCIe Root Complex cont !! 7 title: DesignWare based PCIe controller on Rockchip SoCs
8 8
9 maintainers: 9 maintainers:
10 - Shawn Lin <shawn.lin@rock-chips.com> 10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de> 12 - Heiko Stuebner <heiko@sntech.de>
13 13
14 description: |+ 14 description: |+
15 RK3568 SoC PCIe Root Complex controller is b !! 15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common pro 16 PCIe IP and thus inherits all the common properties defined in
17 snps,dw-pcie.yaml. !! 17 designware-pcie.txt.
18 18
19 allOf: 19 allOf:
20 - $ref: /schemas/pci/snps,dw-pcie.yaml# !! 20 - $ref: /schemas/pci/pci-bus.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common !! 21
>> 22 # We need a select here so we don't match all nodes with 'snps,dw-pcie'
>> 23 select:
>> 24 properties:
>> 25 compatible:
>> 26 contains:
>> 27 const: rockchip,rk3568-pcie
>> 28 required:
>> 29 - compatible
22 30
23 properties: 31 properties:
24 compatible: 32 compatible:
25 oneOf: !! 33 items:
26 - const: rockchip,rk3568-pcie 34 - const: rockchip,rk3568-pcie
27 - items: !! 35 - const: snps,dw-pcie
28 - enum: <<
29 - rockchip,rk3588-pcie <<
30 - const: rockchip,rk3568-pcie <<
31 36
32 reg: 37 reg:
33 items: 38 items:
34 - description: Data Bus Interface (DBI) 39 - description: Data Bus Interface (DBI) registers
35 - description: Rockchip designed configu 40 - description: Rockchip designed configuration registers
36 - description: Config registers 41 - description: Config registers
37 42
38 reg-names: 43 reg-names:
39 items: 44 items:
40 - const: dbi 45 - const: dbi
41 - const: apb 46 - const: apb
42 - const: config 47 - const: config
43 48
44 legacy-interrupt-controller: !! 49 clocks:
45 description: Interrupt controller node for !! 50 items:
46 type: object !! 51 - description: AHB clock for PCIe master
47 additionalProperties: false !! 52 - description: AHB clock for PCIe slave
48 properties: !! 53 - description: AHB clock for PCIe dbi
49 "#address-cells": !! 54 - description: APB clock for PCIe
50 const: 0 !! 55 - description: Auxiliary clock for PCIe
51 !! 56
52 "#interrupt-cells": !! 57 clock-names:
53 const: 1 !! 58 items:
54 !! 59 - const: aclk_mst
55 interrupt-controller: true !! 60 - const: aclk_slv
56 !! 61 - const: aclk_dbi
57 interrupts: !! 62 - const: pclk
58 items: !! 63 - const: aux
59 - description: combined legacy inter <<
60 required: <<
61 - "#address-cells" <<
62 - "#interrupt-cells" <<
63 - interrupt-controller <<
64 - interrupts <<
65 64
66 msi-map: true 65 msi-map: true
67 66
>> 67 num-lanes: true
>> 68
>> 69 phys:
>> 70 maxItems: 1
>> 71
>> 72 phy-names:
>> 73 const: pcie-phy
>> 74
>> 75 power-domains:
>> 76 maxItems: 1
>> 77
68 ranges: 78 ranges:
69 minItems: 2 !! 79 maxItems: 2
70 maxItems: 3 !! 80
>> 81 resets:
>> 82 maxItems: 1
>> 83
>> 84 reset-names:
>> 85 const: pipe
71 86
72 vpcie3v3-supply: true 87 vpcie3v3-supply: true
73 88
74 required: 89 required:
>> 90 - compatible
>> 91 - reg
>> 92 - reg-names
>> 93 - clocks
>> 94 - clock-names
75 - msi-map 95 - msi-map
>> 96 - num-lanes
>> 97 - phys
>> 98 - phy-names
>> 99 - power-domains
>> 100 - resets
>> 101 - reset-names
76 102
77 unevaluatedProperties: false 103 unevaluatedProperties: false
78 104
79 examples: 105 examples:
80 - | 106 - |
81 #include <dt-bindings/interrupt-controller <<
82 107
83 bus { 108 bus {
84 #address-cells = <2>; 109 #address-cells = <2>;
85 #size-cells = <2>; 110 #size-cells = <2>;
86 111
87 pcie3x2: pcie@fe280000 { 112 pcie3x2: pcie@fe280000 {
88 compatible = "rockchip,rk3568-pcie !! 113 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
89 reg = <0x3 0xc0800000 0x0 0x390000 114 reg = <0x3 0xc0800000 0x0 0x390000>,
90 <0x0 0xfe280000 0x0 0x10000> 115 <0x0 0xfe280000 0x0 0x10000>,
91 <0x3 0x80000000 0x0 0x100000 116 <0x3 0x80000000 0x0 0x100000>;
92 reg-names = "dbi", "apb", "config" 117 reg-names = "dbi", "apb", "config";
93 bus-range = <0x20 0x2f>; 118 bus-range = <0x20 0x2f>;
94 clocks = <&cru 143>, <&cru 144>, 119 clocks = <&cru 143>, <&cru 144>,
95 <&cru 145>, <&cru 146>, 120 <&cru 145>, <&cru 146>,
96 <&cru 147>; 121 <&cru 147>;
97 clock-names = "aclk_mst", "aclk_sl 122 clock-names = "aclk_mst", "aclk_slv",
98 "aclk_dbi", "pclk", 123 "aclk_dbi", "pclk",
99 "aux"; 124 "aux";
100 device_type = "pci"; 125 device_type = "pci";
101 interrupts = <GIC_SPI 160 IRQ_TYPE <<
102 <GIC_SPI 159 IRQ_TYPE <<
103 <GIC_SPI 158 IRQ_TYPE <<
104 <GIC_SPI 157 IRQ_TYPE <<
105 <GIC_SPI 156 IRQ_TYPE <<
106 interrupt-names = "sys", "pmc", "m <<
107 linux,pci-domain = <2>; 126 linux,pci-domain = <2>;
108 max-link-speed = <2>; 127 max-link-speed = <2>;
109 msi-map = <0x2000 &its 0x2000 0x10 128 msi-map = <0x2000 &its 0x2000 0x1000>;
110 num-lanes = <2>; 129 num-lanes = <2>;
111 phys = <&pcie30phy>; 130 phys = <&pcie30phy>;
112 phy-names = "pcie-phy"; 131 phy-names = "pcie-phy";
113 power-domains = <&power 15>; 132 power-domains = <&power 15>;
114 ranges = <0x81000000 0x0 0x8080000 133 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x8090000 134 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
116 resets = <&cru 193>; 135 resets = <&cru 193>;
117 reset-names = "pipe"; 136 reset-names = "pipe";
118 #address-cells = <3>; 137 #address-cells = <3>;
119 #size-cells = <2>; 138 #size-cells = <2>;
120 <<
121 legacy-interrupt-controller { <<
122 interrupt-controller; <<
123 #address-cells = <0>; <<
124 #interrupt-cells = <1>; <<
125 interrupt-parent = <&gic>; <<
126 interrupts = <GIC_SPI 72 IRQ_T <<
127 }; <<
128 }; 139 };
129 }; 140 };
130 ... 141 ...
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