1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/rockchi 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: DesignWare based PCIe Root Complex cont !! 7 title: DesignWare based PCIe controller on Rockchip SoCs
8 8
9 maintainers: 9 maintainers:
10 - Shawn Lin <shawn.lin@rock-chips.com> 10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de> 12 - Heiko Stuebner <heiko@sntech.de>
13 13
14 description: |+ 14 description: |+
15 RK3568 SoC PCIe Root Complex controller is b !! 15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common pro 16 PCIe IP and thus inherits all the common properties defined in
17 snps,dw-pcie.yaml. 17 snps,dw-pcie.yaml.
18 18
19 allOf: 19 allOf:
20 - $ref: /schemas/pci/snps,dw-pcie.yaml# 20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common <<
22 21
23 properties: 22 properties:
24 compatible: 23 compatible:
25 oneOf: 24 oneOf:
26 - const: rockchip,rk3568-pcie 25 - const: rockchip,rk3568-pcie
27 - items: 26 - items:
28 - enum: 27 - enum:
29 - rockchip,rk3588-pcie 28 - rockchip,rk3588-pcie
30 - const: rockchip,rk3568-pcie 29 - const: rockchip,rk3568-pcie
31 30
32 reg: 31 reg:
33 items: 32 items:
34 - description: Data Bus Interface (DBI) 33 - description: Data Bus Interface (DBI) registers
35 - description: Rockchip designed configu 34 - description: Rockchip designed configuration registers
36 - description: Config registers 35 - description: Config registers
37 36
38 reg-names: 37 reg-names:
39 items: 38 items:
40 - const: dbi 39 - const: dbi
41 - const: apb 40 - const: apb
42 - const: config 41 - const: config
43 42
44 legacy-interrupt-controller: !! 43 clocks:
45 description: Interrupt controller node for !! 44 minItems: 5
46 type: object !! 45 items:
47 additionalProperties: false !! 46 - description: AHB clock for PCIe master
48 properties: !! 47 - description: AHB clock for PCIe slave
49 "#address-cells": !! 48 - description: AHB clock for PCIe dbi
50 const: 0 !! 49 - description: APB clock for PCIe
51 !! 50 - description: Auxiliary clock for PCIe
52 "#interrupt-cells": !! 51 - description: PIPE clock
53 const: 1 !! 52
54 !! 53 clock-names:
55 interrupt-controller: true !! 54 minItems: 5
56 !! 55 items:
57 interrupts: !! 56 - const: aclk_mst
58 items: !! 57 - const: aclk_slv
59 - description: combined legacy inter !! 58 - const: aclk_dbi
60 required: !! 59 - const: pclk
61 - "#address-cells" !! 60 - const: aux
62 - "#interrupt-cells" !! 61 - const: pipe
63 - interrupt-controller <<
64 - interrupts <<
65 62
66 msi-map: true 63 msi-map: true
67 64
>> 65 num-lanes: true
>> 66
>> 67 phys:
>> 68 maxItems: 1
>> 69
>> 70 phy-names:
>> 71 const: pcie-phy
>> 72
>> 73 power-domains:
>> 74 maxItems: 1
>> 75
68 ranges: 76 ranges:
69 minItems: 2 77 minItems: 2
70 maxItems: 3 78 maxItems: 3
71 79
>> 80 resets:
>> 81 minItems: 1
>> 82 maxItems: 2
>> 83
>> 84 reset-names:
>> 85 oneOf:
>> 86 - const: pipe
>> 87 - items:
>> 88 - const: pwr
>> 89 - const: pipe
>> 90
72 vpcie3v3-supply: true 91 vpcie3v3-supply: true
73 92
74 required: 93 required:
>> 94 - compatible
>> 95 - reg
>> 96 - reg-names
>> 97 - clocks
>> 98 - clock-names
75 - msi-map 99 - msi-map
>> 100 - num-lanes
>> 101 - phys
>> 102 - phy-names
>> 103 - power-domains
>> 104 - resets
>> 105 - reset-names
76 106
77 unevaluatedProperties: false 107 unevaluatedProperties: false
78 108
79 examples: 109 examples:
80 - | 110 - |
81 #include <dt-bindings/interrupt-controller <<
82 111
83 bus { 112 bus {
84 #address-cells = <2>; 113 #address-cells = <2>;
85 #size-cells = <2>; 114 #size-cells = <2>;
86 115
87 pcie3x2: pcie@fe280000 { 116 pcie3x2: pcie@fe280000 {
88 compatible = "rockchip,rk3568-pcie 117 compatible = "rockchip,rk3568-pcie";
89 reg = <0x3 0xc0800000 0x0 0x390000 118 reg = <0x3 0xc0800000 0x0 0x390000>,
90 <0x0 0xfe280000 0x0 0x10000> 119 <0x0 0xfe280000 0x0 0x10000>,
91 <0x3 0x80000000 0x0 0x100000 120 <0x3 0x80000000 0x0 0x100000>;
92 reg-names = "dbi", "apb", "config" 121 reg-names = "dbi", "apb", "config";
93 bus-range = <0x20 0x2f>; 122 bus-range = <0x20 0x2f>;
94 clocks = <&cru 143>, <&cru 144>, 123 clocks = <&cru 143>, <&cru 144>,
95 <&cru 145>, <&cru 146>, 124 <&cru 145>, <&cru 146>,
96 <&cru 147>; 125 <&cru 147>;
97 clock-names = "aclk_mst", "aclk_sl 126 clock-names = "aclk_mst", "aclk_slv",
98 "aclk_dbi", "pclk", 127 "aclk_dbi", "pclk",
99 "aux"; 128 "aux";
100 device_type = "pci"; 129 device_type = "pci";
101 interrupts = <GIC_SPI 160 IRQ_TYPE <<
102 <GIC_SPI 159 IRQ_TYPE <<
103 <GIC_SPI 158 IRQ_TYPE <<
104 <GIC_SPI 157 IRQ_TYPE <<
105 <GIC_SPI 156 IRQ_TYPE <<
106 interrupt-names = "sys", "pmc", "m <<
107 linux,pci-domain = <2>; 130 linux,pci-domain = <2>;
108 max-link-speed = <2>; 131 max-link-speed = <2>;
109 msi-map = <0x2000 &its 0x2000 0x10 132 msi-map = <0x2000 &its 0x2000 0x1000>;
110 num-lanes = <2>; 133 num-lanes = <2>;
111 phys = <&pcie30phy>; 134 phys = <&pcie30phy>;
112 phy-names = "pcie-phy"; 135 phy-names = "pcie-phy";
113 power-domains = <&power 15>; 136 power-domains = <&power 15>;
114 ranges = <0x81000000 0x0 0x8080000 137 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x8090000 138 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
116 resets = <&cru 193>; 139 resets = <&cru 193>;
117 reset-names = "pipe"; 140 reset-names = "pipe";
118 #address-cells = <3>; 141 #address-cells = <3>;
119 #size-cells = <2>; 142 #size-cells = <2>;
120 <<
121 legacy-interrupt-controller { <<
122 interrupt-controller; <<
123 #address-cells = <0>; <<
124 #interrupt-cells = <1>; <<
125 interrupt-parent = <&gic>; <<
126 interrupts = <GIC_SPI 72 IRQ_T <<
127 }; <<
128 }; 143 };
129 }; 144 };
130 ... 145 ...
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