1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/rockchi 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: DesignWare based PCIe Root Complex cont !! 7 title: DesignWare based PCIe controller on Rockchip SoCs
8 8
9 maintainers: 9 maintainers:
10 - Shawn Lin <shawn.lin@rock-chips.com> 10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de> 12 - Heiko Stuebner <heiko@sntech.de>
13 13
14 description: |+ 14 description: |+
15 RK3568 SoC PCIe Root Complex controller is b !! 15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common pro 16 PCIe IP and thus inherits all the common properties defined in
17 snps,dw-pcie.yaml. 17 snps,dw-pcie.yaml.
18 18
19 allOf: 19 allOf:
20 - $ref: /schemas/pci/snps,dw-pcie.yaml# 20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common <<
22 21
23 properties: 22 properties:
24 compatible: 23 compatible:
25 oneOf: 24 oneOf:
26 - const: rockchip,rk3568-pcie 25 - const: rockchip,rk3568-pcie
27 - items: 26 - items:
28 - enum: 27 - enum:
29 - rockchip,rk3588-pcie 28 - rockchip,rk3588-pcie
30 - const: rockchip,rk3568-pcie 29 - const: rockchip,rk3568-pcie
31 30
32 reg: 31 reg:
33 items: 32 items:
34 - description: Data Bus Interface (DBI) 33 - description: Data Bus Interface (DBI) registers
35 - description: Rockchip designed configu 34 - description: Rockchip designed configuration registers
36 - description: Config registers 35 - description: Config registers
37 36
38 reg-names: 37 reg-names:
39 items: 38 items:
40 - const: dbi 39 - const: dbi
41 - const: apb 40 - const: apb
42 - const: config 41 - const: config
43 42
>> 43 clocks:
>> 44 minItems: 5
>> 45 items:
>> 46 - description: AHB clock for PCIe master
>> 47 - description: AHB clock for PCIe slave
>> 48 - description: AHB clock for PCIe dbi
>> 49 - description: APB clock for PCIe
>> 50 - description: Auxiliary clock for PCIe
>> 51 - description: PIPE clock
>> 52
>> 53 clock-names:
>> 54 minItems: 5
>> 55 items:
>> 56 - const: aclk_mst
>> 57 - const: aclk_slv
>> 58 - const: aclk_dbi
>> 59 - const: pclk
>> 60 - const: aux
>> 61 - const: pipe
>> 62
>> 63 interrupts:
>> 64 items:
>> 65 - description:
>> 66 Combined system interrupt, which is used to signal the following
>> 67 interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
>> 68 hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
>> 69 edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
>> 70 - description:
>> 71 Combined PM interrupt, which is used to signal the following
>> 72 interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
>> 73 linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
>> 74 linkst_out_l0s, pm_dstate_update
>> 75 - description:
>> 76 Combined message interrupt, which is used to signal the following
>> 77 interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
>> 78 pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
>> 79 - description:
>> 80 Combined legacy interrupt, which is used to signal the following
>> 81 interrupts - inta, intb, intc, intd
>> 82 - description:
>> 83 Combined error interrupt, which is used to signal the following
>> 84 interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
>> 85 tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
>> 86 nf_err_rx, f_err_rx, radm_qoverflow
>> 87
>> 88 interrupt-names:
>> 89 items:
>> 90 - const: sys
>> 91 - const: pmc
>> 92 - const: msg
>> 93 - const: legacy
>> 94 - const: err
>> 95
44 legacy-interrupt-controller: 96 legacy-interrupt-controller:
45 description: Interrupt controller node for 97 description: Interrupt controller node for handling legacy PCI interrupts.
46 type: object 98 type: object
47 additionalProperties: false 99 additionalProperties: false
48 properties: 100 properties:
49 "#address-cells": 101 "#address-cells":
50 const: 0 102 const: 0
51 103
52 "#interrupt-cells": 104 "#interrupt-cells":
53 const: 1 105 const: 1
54 106
55 interrupt-controller: true 107 interrupt-controller: true
56 108
57 interrupts: 109 interrupts:
58 items: 110 items:
59 - description: combined legacy inter 111 - description: combined legacy interrupt
60 required: 112 required:
61 - "#address-cells" 113 - "#address-cells"
62 - "#interrupt-cells" 114 - "#interrupt-cells"
63 - interrupt-controller 115 - interrupt-controller
64 - interrupts 116 - interrupts
65 117
66 msi-map: true 118 msi-map: true
67 119
>> 120 num-lanes: true
>> 121
>> 122 phys:
>> 123 maxItems: 1
>> 124
>> 125 phy-names:
>> 126 const: pcie-phy
>> 127
>> 128 power-domains:
>> 129 maxItems: 1
>> 130
68 ranges: 131 ranges:
69 minItems: 2 132 minItems: 2
70 maxItems: 3 133 maxItems: 3
71 134
>> 135 resets:
>> 136 minItems: 1
>> 137 maxItems: 2
>> 138
>> 139 reset-names:
>> 140 oneOf:
>> 141 - const: pipe
>> 142 - items:
>> 143 - const: pwr
>> 144 - const: pipe
>> 145
72 vpcie3v3-supply: true 146 vpcie3v3-supply: true
73 147
74 required: 148 required:
>> 149 - compatible
>> 150 - reg
>> 151 - reg-names
>> 152 - clocks
>> 153 - clock-names
75 - msi-map 154 - msi-map
>> 155 - num-lanes
>> 156 - phys
>> 157 - phy-names
>> 158 - power-domains
>> 159 - resets
>> 160 - reset-names
76 161
77 unevaluatedProperties: false 162 unevaluatedProperties: false
78 163
79 examples: 164 examples:
80 - | 165 - |
81 #include <dt-bindings/interrupt-controller 166 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 167
83 bus { 168 bus {
84 #address-cells = <2>; 169 #address-cells = <2>;
85 #size-cells = <2>; 170 #size-cells = <2>;
86 171
87 pcie3x2: pcie@fe280000 { 172 pcie3x2: pcie@fe280000 {
88 compatible = "rockchip,rk3568-pcie 173 compatible = "rockchip,rk3568-pcie";
89 reg = <0x3 0xc0800000 0x0 0x390000 174 reg = <0x3 0xc0800000 0x0 0x390000>,
90 <0x0 0xfe280000 0x0 0x10000> 175 <0x0 0xfe280000 0x0 0x10000>,
91 <0x3 0x80000000 0x0 0x100000 176 <0x3 0x80000000 0x0 0x100000>;
92 reg-names = "dbi", "apb", "config" 177 reg-names = "dbi", "apb", "config";
93 bus-range = <0x20 0x2f>; 178 bus-range = <0x20 0x2f>;
94 clocks = <&cru 143>, <&cru 144>, 179 clocks = <&cru 143>, <&cru 144>,
95 <&cru 145>, <&cru 146>, 180 <&cru 145>, <&cru 146>,
96 <&cru 147>; 181 <&cru 147>;
97 clock-names = "aclk_mst", "aclk_sl 182 clock-names = "aclk_mst", "aclk_slv",
98 "aclk_dbi", "pclk", 183 "aclk_dbi", "pclk",
99 "aux"; 184 "aux";
100 device_type = "pci"; 185 device_type = "pci";
101 interrupts = <GIC_SPI 160 IRQ_TYPE 186 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 159 IRQ_TYPE 187 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 158 IRQ_TYPE 188 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 157 IRQ_TYPE 189 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 156 IRQ_TYPE 190 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-names = "sys", "pmc", "m 191 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
107 linux,pci-domain = <2>; 192 linux,pci-domain = <2>;
108 max-link-speed = <2>; 193 max-link-speed = <2>;
109 msi-map = <0x2000 &its 0x2000 0x10 194 msi-map = <0x2000 &its 0x2000 0x1000>;
110 num-lanes = <2>; 195 num-lanes = <2>;
111 phys = <&pcie30phy>; 196 phys = <&pcie30phy>;
112 phy-names = "pcie-phy"; 197 phy-names = "pcie-phy";
113 power-domains = <&power 15>; 198 power-domains = <&power 15>;
114 ranges = <0x81000000 0x0 0x8080000 199 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x8090000 200 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
116 resets = <&cru 193>; 201 resets = <&cru 193>;
117 reset-names = "pipe"; 202 reset-names = "pipe";
118 #address-cells = <3>; 203 #address-cells = <3>;
119 #size-cells = <2>; 204 #size-cells = <2>;
120 205
121 legacy-interrupt-controller { 206 legacy-interrupt-controller {
122 interrupt-controller; 207 interrupt-controller;
123 #address-cells = <0>; 208 #address-cells = <0>;
124 #interrupt-cells = <1>; 209 #interrupt-cells = <1>;
125 interrupt-parent = <&gic>; 210 interrupt-parent = <&gic>;
126 interrupts = <GIC_SPI 72 IRQ_T 211 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
127 }; 212 };
128 }; 213 };
129 }; 214 };
130 ... 215 ...
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