1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/rockchi 4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: DesignWare based PCIe Root Complex cont !! 7 title: DesignWare based PCIe controller on Rockchip SoCs
8 8
9 maintainers: 9 maintainers:
10 - Shawn Lin <shawn.lin@rock-chips.com> 10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de> 12 - Heiko Stuebner <heiko@sntech.de>
13 13
14 description: |+ 14 description: |+
15 RK3568 SoC PCIe Root Complex controller is b !! 15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common pro 16 PCIe IP and thus inherits all the common properties defined in
17 snps,dw-pcie.yaml. 17 snps,dw-pcie.yaml.
18 18
19 allOf: 19 allOf:
20 - $ref: /schemas/pci/snps,dw-pcie.yaml# 20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common <<
22 21
23 properties: 22 properties:
24 compatible: 23 compatible:
25 oneOf: 24 oneOf:
26 - const: rockchip,rk3568-pcie 25 - const: rockchip,rk3568-pcie
27 - items: 26 - items:
28 - enum: 27 - enum:
29 - rockchip,rk3588-pcie 28 - rockchip,rk3588-pcie
30 - const: rockchip,rk3568-pcie 29 - const: rockchip,rk3568-pcie
31 30
32 reg: 31 reg:
33 items: 32 items:
34 - description: Data Bus Interface (DBI) 33 - description: Data Bus Interface (DBI) registers
35 - description: Rockchip designed configu 34 - description: Rockchip designed configuration registers
36 - description: Config registers 35 - description: Config registers
37 36
38 reg-names: 37 reg-names:
39 items: 38 items:
40 - const: dbi 39 - const: dbi
41 - const: apb 40 - const: apb
42 - const: config 41 - const: config
43 42
>> 43 clocks:
>> 44 minItems: 5
>> 45 items:
>> 46 - description: AHB clock for PCIe master
>> 47 - description: AHB clock for PCIe slave
>> 48 - description: AHB clock for PCIe dbi
>> 49 - description: APB clock for PCIe
>> 50 - description: Auxiliary clock for PCIe
>> 51 - description: PIPE clock
>> 52 - description: Reference clock for PCIe
>> 53
>> 54 clock-names:
>> 55 minItems: 5
>> 56 items:
>> 57 - const: aclk_mst
>> 58 - const: aclk_slv
>> 59 - const: aclk_dbi
>> 60 - const: pclk
>> 61 - const: aux
>> 62 - const: pipe
>> 63 - const: ref
>> 64
>> 65 interrupts:
>> 66 items:
>> 67 - description:
>> 68 Combined system interrupt, which is used to signal the following
>> 69 interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
>> 70 hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
>> 71 edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
>> 72 - description:
>> 73 Combined PM interrupt, which is used to signal the following
>> 74 interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
>> 75 linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
>> 76 linkst_out_l0s, pm_dstate_update
>> 77 - description:
>> 78 Combined message interrupt, which is used to signal the following
>> 79 interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
>> 80 pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
>> 81 - description:
>> 82 Combined legacy interrupt, which is used to signal the following
>> 83 interrupts - inta, intb, intc, intd
>> 84 - description:
>> 85 Combined error interrupt, which is used to signal the following
>> 86 interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
>> 87 tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
>> 88 nf_err_rx, f_err_rx, radm_qoverflow
>> 89
>> 90 interrupt-names:
>> 91 items:
>> 92 - const: sys
>> 93 - const: pmc
>> 94 - const: msg
>> 95 - const: legacy
>> 96 - const: err
>> 97
44 legacy-interrupt-controller: 98 legacy-interrupt-controller:
45 description: Interrupt controller node for 99 description: Interrupt controller node for handling legacy PCI interrupts.
46 type: object 100 type: object
47 additionalProperties: false 101 additionalProperties: false
48 properties: 102 properties:
49 "#address-cells": 103 "#address-cells":
50 const: 0 104 const: 0
51 105
52 "#interrupt-cells": 106 "#interrupt-cells":
53 const: 1 107 const: 1
54 108
55 interrupt-controller: true 109 interrupt-controller: true
56 110
57 interrupts: 111 interrupts:
58 items: 112 items:
59 - description: combined legacy inter 113 - description: combined legacy interrupt
60 required: 114 required:
61 - "#address-cells" 115 - "#address-cells"
62 - "#interrupt-cells" 116 - "#interrupt-cells"
63 - interrupt-controller 117 - interrupt-controller
64 - interrupts 118 - interrupts
65 119
66 msi-map: true 120 msi-map: true
67 121
>> 122 num-lanes: true
>> 123
>> 124 phys:
>> 125 maxItems: 1
>> 126
>> 127 phy-names:
>> 128 const: pcie-phy
>> 129
>> 130 power-domains:
>> 131 maxItems: 1
>> 132
68 ranges: 133 ranges:
69 minItems: 2 134 minItems: 2
70 maxItems: 3 135 maxItems: 3
71 136
>> 137 resets:
>> 138 minItems: 1
>> 139 maxItems: 2
>> 140
>> 141 reset-names:
>> 142 oneOf:
>> 143 - const: pipe
>> 144 - items:
>> 145 - const: pwr
>> 146 - const: pipe
>> 147
72 vpcie3v3-supply: true 148 vpcie3v3-supply: true
73 149
74 required: 150 required:
>> 151 - compatible
>> 152 - reg
>> 153 - reg-names
>> 154 - clocks
>> 155 - clock-names
75 - msi-map 156 - msi-map
>> 157 - num-lanes
>> 158 - phys
>> 159 - phy-names
>> 160 - power-domains
>> 161 - resets
>> 162 - reset-names
76 163
77 unevaluatedProperties: false 164 unevaluatedProperties: false
78 165
79 examples: 166 examples:
80 - | 167 - |
81 #include <dt-bindings/interrupt-controller 168 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 169
83 bus { 170 bus {
84 #address-cells = <2>; 171 #address-cells = <2>;
85 #size-cells = <2>; 172 #size-cells = <2>;
86 173
87 pcie3x2: pcie@fe280000 { 174 pcie3x2: pcie@fe280000 {
88 compatible = "rockchip,rk3568-pcie 175 compatible = "rockchip,rk3568-pcie";
89 reg = <0x3 0xc0800000 0x0 0x390000 176 reg = <0x3 0xc0800000 0x0 0x390000>,
90 <0x0 0xfe280000 0x0 0x10000> 177 <0x0 0xfe280000 0x0 0x10000>,
91 <0x3 0x80000000 0x0 0x100000 178 <0x3 0x80000000 0x0 0x100000>;
92 reg-names = "dbi", "apb", "config" 179 reg-names = "dbi", "apb", "config";
93 bus-range = <0x20 0x2f>; 180 bus-range = <0x20 0x2f>;
94 clocks = <&cru 143>, <&cru 144>, 181 clocks = <&cru 143>, <&cru 144>,
95 <&cru 145>, <&cru 146>, 182 <&cru 145>, <&cru 146>,
96 <&cru 147>; 183 <&cru 147>;
97 clock-names = "aclk_mst", "aclk_sl 184 clock-names = "aclk_mst", "aclk_slv",
98 "aclk_dbi", "pclk", 185 "aclk_dbi", "pclk",
99 "aux"; 186 "aux";
100 device_type = "pci"; 187 device_type = "pci";
101 interrupts = <GIC_SPI 160 IRQ_TYPE 188 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 159 IRQ_TYPE 189 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 158 IRQ_TYPE 190 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 157 IRQ_TYPE 191 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 156 IRQ_TYPE 192 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-names = "sys", "pmc", "m 193 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
107 linux,pci-domain = <2>; 194 linux,pci-domain = <2>;
108 max-link-speed = <2>; 195 max-link-speed = <2>;
109 msi-map = <0x2000 &its 0x2000 0x10 196 msi-map = <0x2000 &its 0x2000 0x1000>;
110 num-lanes = <2>; 197 num-lanes = <2>;
111 phys = <&pcie30phy>; 198 phys = <&pcie30phy>;
112 phy-names = "pcie-phy"; 199 phy-names = "pcie-phy";
113 power-domains = <&power 15>; 200 power-domains = <&power 15>;
114 ranges = <0x81000000 0x0 0x8080000 201 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x8090000 202 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
116 resets = <&cru 193>; 203 resets = <&cru 193>;
117 reset-names = "pipe"; 204 reset-names = "pipe";
118 #address-cells = <3>; 205 #address-cells = <3>;
119 #size-cells = <2>; 206 #size-cells = <2>;
120 207
121 legacy-interrupt-controller { 208 legacy-interrupt-controller {
122 interrupt-controller; 209 interrupt-controller;
123 #address-cells = <0>; 210 #address-cells = <0>;
124 #interrupt-cells = <1>; 211 #interrupt-cells = <1>;
125 interrupt-parent = <&gic>; 212 interrupt-parent = <&gic>;
126 interrupts = <GIC_SPI 72 IRQ_T 213 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
127 }; 214 };
128 }; 215 };
129 }; 216 };
130 ... 217 ...
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