1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorpo 2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65 5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: TI AM65 PCI Endpoint 8 title: TI AM65 PCI Endpoint
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 allOf: 13 allOf:
14 - $ref: pci-ep.yaml# 14 - $ref: pci-ep.yaml#
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - ti,am654-pcie-ep 19 - ti,am654-pcie-ep
20 20
21 reg: 21 reg:
22 maxItems: 4 22 maxItems: 4
23 23
24 reg-names: 24 reg-names:
25 items: 25 items:
26 - const: app 26 - const: app
27 - const: dbics 27 - const: dbics
28 - const: addr_space 28 - const: addr_space
29 - const: atu 29 - const: atu
30 30
31 power-domains: 31 power-domains:
32 maxItems: 1 32 maxItems: 1
33 33
34 ti,syscon-pcie-mode: 34 ti,syscon-pcie-mode:
35 $ref: /schemas/types.yaml#/definitions/pha <<
36 items: <<
37 - items: <<
38 - description: Phandle to the SYSCON <<
39 - description: pcie_ctrl register of <<
40 description: Phandle to the SYSCON entry r 35 description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
>> 36 $ref: /schemas/types.yaml#/definitions/phandle
41 37
42 interrupts: 38 interrupts:
43 minItems: 1 39 minItems: 1
44 40
45 dma-coherent: true 41 dma-coherent: true
46 42
47 required: 43 required:
48 - compatible 44 - compatible
49 - reg 45 - reg
50 - reg-names 46 - reg-names
51 - max-link-speed 47 - max-link-speed
52 - power-domains 48 - power-domains
53 - ti,syscon-pcie-mode 49 - ti,syscon-pcie-mode
54 - dma-coherent 50 - dma-coherent
55 51
56 unevaluatedProperties: false 52 unevaluatedProperties: false
57 53
58 examples: 54 examples:
59 - | 55 - |
60 #include <dt-bindings/interrupt-controller 56 #include <dt-bindings/interrupt-controller/arm-gic.h>
61 #include <dt-bindings/interrupt-controller 57 #include <dt-bindings/interrupt-controller/irq.h>
62 #include <dt-bindings/soc/ti,sci_pm_domain 58 #include <dt-bindings/soc/ti,sci_pm_domain.h>
63 59
64 pcie0_ep: pcie-ep@5500000 { 60 pcie0_ep: pcie-ep@5500000 {
65 compatible = "ti,am654-pcie-ep"; 61 compatible = "ti,am654-pcie-ep";
66 reg = <0x5500000 0x1000>, 62 reg = <0x5500000 0x1000>,
67 <0x5501000 0x1000>, 63 <0x5501000 0x1000>,
68 <0x10000000 0x8000000>, 64 <0x10000000 0x8000000>,
69 <0x5506000 0x1000>; 65 <0x5506000 0x1000>;
70 reg-names = "app", "dbics", "addr_spac 66 reg-names = "app", "dbics", "addr_space", "atu";
71 power-domains = <&k3_pds 120 TI_SCI_PD 67 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
72 ti,syscon-pcie-mode = <&scm_conf 0x406 !! 68 ti,syscon-pcie-mode = <&pcie0_mode>;
>> 69 num-ib-windows = <16>;
>> 70 num-ob-windows = <16>;
73 max-link-speed = <2>; 71 max-link-speed = <2>;
74 dma-coherent; 72 dma-coherent;
75 interrupts = <GIC_SPI 340 IRQ_TYPE_EDG 73 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
76 }; 74 };
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