1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorpo 2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65 5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: TI AM65 PCI Host 8 title: TI AM65 PCI Host
9 9
10 maintainers: 10 maintainers:
11 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Kishon Vijay Abraham I <kishon@ti.com>
12 12
13 allOf: 13 allOf:
14 - $ref: /schemas/pci/pci-host-bridge.yaml# 14 - $ref: /schemas/pci/pci-host-bridge.yaml#
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - ti,am654-pcie-rc 19 - ti,am654-pcie-rc
20 - ti,keystone-pcie 20 - ti,keystone-pcie
21 21
22 reg: 22 reg:
23 maxItems: 4 23 maxItems: 4
24 24
25 reg-names: 25 reg-names:
26 items: 26 items:
27 - const: app 27 - const: app
28 - const: dbics 28 - const: dbics
29 - const: config 29 - const: config
30 - const: atu 30 - const: atu
31 31
32 interrupts: 32 interrupts:
33 maxItems: 1 33 maxItems: 1
34 34
35 power-domains: 35 power-domains:
36 maxItems: 1 36 maxItems: 1
37 37
38 ti,syscon-pcie-id: 38 ti,syscon-pcie-id:
39 $ref: /schemas/types.yaml#/definitions/pha 39 $ref: /schemas/types.yaml#/definitions/phandle-array
40 items: 40 items:
41 - items: 41 - items:
42 - description: Phandle to the SYSCON 42 - description: Phandle to the SYSCON entry
43 - description: pcie_device_id regist 43 - description: pcie_device_id register offset within SYSCON
44 description: Phandle to the SYSCON entry r 44 description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
45 45
46 ti,syscon-pcie-mode: 46 ti,syscon-pcie-mode:
47 $ref: /schemas/types.yaml#/definitions/pha 47 $ref: /schemas/types.yaml#/definitions/phandle-array
48 items: 48 items:
49 - items: 49 - items:
50 - description: Phandle to the SYSCON 50 - description: Phandle to the SYSCON entry
51 - description: pcie_ctrl register of 51 - description: pcie_ctrl register offset within SYSCON
52 description: Phandle to the SYSCON entry r 52 description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
53 53
54 msi-map: true 54 msi-map: true
55 55
56 dma-coherent: true 56 dma-coherent: true
57 57
58 num-viewport: 58 num-viewport:
59 $ref: /schemas/types.yaml#/definitions/uin 59 $ref: /schemas/types.yaml#/definitions/uint32
60 60
61 phys: 61 phys:
62 description: per-lane PHYs 62 description: per-lane PHYs
63 minItems: 1 63 minItems: 1
64 maxItems: 2 64 maxItems: 2
65 65
66 phy-names: 66 phy-names:
67 minItems: 1 67 minItems: 1
68 maxItems: 2 68 maxItems: 2
69 items: 69 items:
70 pattern: '^pcie-phy[0-1]$' 70 pattern: '^pcie-phy[0-1]$'
71 71
72 required: 72 required:
73 - compatible 73 - compatible
74 - reg 74 - reg
75 - reg-names 75 - reg-names
76 - max-link-speed 76 - max-link-speed
77 - ti,syscon-pcie-id 77 - ti,syscon-pcie-id
78 - ti,syscon-pcie-mode 78 - ti,syscon-pcie-mode
79 - ranges 79 - ranges
80 80
81 if: 81 if:
82 properties: 82 properties:
83 compatible: 83 compatible:
84 enum: 84 enum:
85 - ti,am654-pcie-rc 85 - ti,am654-pcie-rc
86 then: 86 then:
87 required: 87 required:
88 - dma-coherent 88 - dma-coherent
89 - power-domains 89 - power-domains
90 - msi-map 90 - msi-map
91 - num-viewport 91 - num-viewport
92 92
93 unevaluatedProperties: false 93 unevaluatedProperties: false
94 94
95 examples: 95 examples:
96 - | 96 - |
97 #include <dt-bindings/interrupt-controller 97 #include <dt-bindings/interrupt-controller/arm-gic.h>
98 #include <dt-bindings/interrupt-controller 98 #include <dt-bindings/interrupt-controller/irq.h>
99 #include <dt-bindings/phy/phy.h> 99 #include <dt-bindings/phy/phy.h>
100 #include <dt-bindings/soc/ti,sci_pm_domain 100 #include <dt-bindings/soc/ti,sci_pm_domain.h>
101 101
102 pcie0_rc: pcie@5500000 { 102 pcie0_rc: pcie@5500000 {
103 compatible = "ti,am654-pcie-rc"; 103 compatible = "ti,am654-pcie-rc";
104 reg = <0x5500000 0x1000>, 104 reg = <0x5500000 0x1000>,
105 <0x5501000 0x1000>, 105 <0x5501000 0x1000>,
106 <0x10000000 0x2000>, 106 <0x10000000 0x2000>,
107 <0x5506000 0x1000>; 107 <0x5506000 0x1000>;
108 reg-names = "app", "dbics", "config", 108 reg-names = "app", "dbics", "config", "atu";
109 power-domains = <&k3_pds 120 TI_SCI_PD 109 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
110 #address-cells = <3>; 110 #address-cells = <3>;
111 #size-cells = <2>; 111 #size-cells = <2>;
112 ranges = <0x81000000 0 0 0x10 112 ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
113 <0x82000000 0 0x10030000 0x10 113 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
114 ti,syscon-pcie-id = <&scm_conf 0x0210> 114 ti,syscon-pcie-id = <&scm_conf 0x0210>;
115 ti,syscon-pcie-mode = <&scm_conf 0x406 115 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
116 bus-range = <0x0 0xff>; 116 bus-range = <0x0 0xff>;
117 num-viewport = <16>; 117 num-viewport = <16>;
118 max-link-speed = <2>; 118 max-link-speed = <2>;
119 dma-coherent; 119 dma-coherent;
120 interrupts = <GIC_SPI 340 IRQ_TYPE_EDG 120 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
121 msi-map = <0x0 &gic_its 0x0 0x10000>; 121 msi-map = <0x0 &gic_its 0x0 0x10000>;
122 device_type = "pci"; 122 device_type = "pci";
123 num-lanes = <1>; 123 num-lanes = <1>;
124 phys = <&serdes0 PHY_TYPE_PCIE 0>; 124 phys = <&serdes0 PHY_TYPE_PCIE 0>;
125 phy-names = "pcie-phy0"; 125 phy-names = "pcie-phy0";
126 }; 126 };
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