1 * AppliedMicro X-Gene PCIe interface 1 * AppliedMicro X-Gene PCIe interface
2 2
3 Required properties: 3 Required properties:
4 - device_type: set to "pci" 4 - device_type: set to "pci"
5 - compatible: should contain "apm,xgene-pcie" 5 - compatible: should contain "apm,xgene-pcie" to identify the core.
6 - reg: A list of physical base address and len 6 - reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for ea 7 registers. Must contain an entry for each entry in the reg-names
8 property. 8 property.
9 - reg-names: Must include the following entrie 9 - reg-names: Must include the following entries:
10 "csr": controller configuration registers. 10 "csr": controller configuration registers.
11 "cfg": PCIe configuration space registers. 11 "cfg": PCIe configuration space registers.
12 - #address-cells: set to <3> 12 - #address-cells: set to <3>
13 - #size-cells: set to <2> 13 - #size-cells: set to <2>
14 - ranges: ranges for the outbound memory, I/O 14 - ranges: ranges for the outbound memory, I/O regions.
15 - dma-ranges: ranges for the inbound memory re 15 - dma-ranges: ranges for the inbound memory regions.
16 - #interrupt-cells: set to <1> 16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map: standa 17 - interrupt-map-mask and interrupt-map: standard PCI properties
18 to define the mapping of the PCIe inte 18 to define the mapping of the PCIe interface to interrupt
19 numbers. 19 numbers.
20 - clocks: from common clock binding: handle to 20 - clocks: from common clock binding: handle to pci clock.
21 21
22 Optional properties: 22 Optional properties:
23 - status: Either "ok" or "disabled". 23 - status: Either "ok" or "disabled".
24 - dma-coherent: Present if DMA operations are 24 - dma-coherent: Present if DMA operations are coherent
25 25
26 Example: 26 Example:
27 27
28 pcie0: pcie@1f2b0000 { 28 pcie0: pcie@1f2b0000 {
29 status = "disabled"; 29 status = "disabled";
30 device_type = "pci"; 30 device_type = "pci";
31 compatible = "apm,xgene-storm- 31 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
32 #interrupt-cells = <1>; 32 #interrupt-cells = <1>;
33 #size-cells = <2>; 33 #size-cells = <2>;
34 #address-cells = <3>; 34 #address-cells = <3>;
35 reg = < 0x00 0x1f2b0000 0x0 0x 35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x 36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
37 reg-names = "csr", "cfg"; 37 reg-names = "csr", "cfg";
38 ranges = <0x01000000 0x00 0x00 38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80 39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0 43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0 44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0 45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
46 0x0 0x0 0x0 0 46 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
47 dma-coherent; 47 dma-coherent;
48 clocks = <&pcie0clk 0>; 48 clocks = <&pcie0clk 0>;
49 }; 49 };
50 50
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