1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,xd 4 $id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx XDMA PL PCIe Root Port Bridge 7 title: Xilinx XDMA PL PCIe Root Port Bridge
8 8
9 maintainers: 9 maintainers:
10 - Thippeswamy Havalige <thippeswamy.havalige@ 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11 11
12 allOf: 12 allOf:
13 - $ref: /schemas/pci/pci-host-bridge.yaml# 13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 enum: !! 17 const: xlnx,xdma-host-3.00
18 - xlnx,xdma-host-3.00 <<
19 - xlnx,qdma-host-3.00 <<
20 18
21 reg: 19 reg:
22 items: !! 20 maxItems: 1
23 - description: configuration region and <<
24 - description: QDMA bridge register. <<
25 minItems: 1 <<
26 <<
27 reg-names: <<
28 items: <<
29 - const: cfg <<
30 - const: breg <<
31 minItems: 1 <<
32 21
33 ranges: 22 ranges:
34 maxItems: 2 23 maxItems: 2
35 24
36 interrupts: 25 interrupts:
37 items: 26 items:
38 - description: interrupt asserted when m 27 - description: interrupt asserted when miscellaneous interrupt is received.
39 - description: msi0 interrupt asserted w 28 - description: msi0 interrupt asserted when an MSI is received.
40 - description: msi1 interrupt asserted w 29 - description: msi1 interrupt asserted when an MSI is received.
41 30
42 interrupt-names: 31 interrupt-names:
43 items: 32 items:
44 - const: misc 33 - const: misc
45 - const: msi0 34 - const: msi0
46 - const: msi1 35 - const: msi1
47 36
48 interrupt-map-mask: 37 interrupt-map-mask:
49 items: 38 items:
50 - const: 0 39 - const: 0
51 - const: 0 40 - const: 0
52 - const: 0 41 - const: 0
53 - const: 7 42 - const: 7
54 43
55 interrupt-map: 44 interrupt-map:
56 maxItems: 4 45 maxItems: 4
57 46
58 "#interrupt-cells": 47 "#interrupt-cells":
59 const: 1 48 const: 1
60 49
61 interrupt-controller: 50 interrupt-controller:
62 description: identifies the node as an int 51 description: identifies the node as an interrupt controller
63 type: object 52 type: object
64 properties: 53 properties:
65 interrupt-controller: true 54 interrupt-controller: true
66 55
67 "#address-cells": 56 "#address-cells":
68 const: 0 57 const: 0
69 58
70 "#interrupt-cells": 59 "#interrupt-cells":
71 const: 1 60 const: 1
72 61
73 required: 62 required:
74 - interrupt-controller 63 - interrupt-controller
75 - "#address-cells" 64 - "#address-cells"
76 - "#interrupt-cells" 65 - "#interrupt-cells"
77 66
78 additionalProperties: false 67 additionalProperties: false
79 68
80 required: 69 required:
81 - compatible 70 - compatible
82 - reg 71 - reg
83 - ranges 72 - ranges
84 - interrupts 73 - interrupts
85 - interrupt-map 74 - interrupt-map
86 - interrupt-map-mask 75 - interrupt-map-mask
87 - "#interrupt-cells" 76 - "#interrupt-cells"
88 - interrupt-controller 77 - interrupt-controller
89 <<
90 if: <<
91 properties: <<
92 compatible: <<
93 contains: <<
94 enum: <<
95 - xlnx,qdma-host-3.00 <<
96 then: <<
97 properties: <<
98 reg: <<
99 minItems: 2 <<
100 reg-names: <<
101 minItems: 2 <<
102 required: <<
103 - reg-names <<
104 else: <<
105 properties: <<
106 reg: <<
107 maxItems: 1 <<
108 reg-names: <<
109 maxItems: 1 <<
110 78
111 unevaluatedProperties: false 79 unevaluatedProperties: false
112 80
113 examples: 81 examples:
114 82
115 - | 83 - |
116 #include <dt-bindings/interrupt-controller 84 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 #include <dt-bindings/interrupt-controller 85 #include <dt-bindings/interrupt-controller/irq.h>
118 86
119 soc { 87 soc {
120 #address-cells = <2>; 88 #address-cells = <2>;
121 #size-cells = <2>; 89 #size-cells = <2>;
122 pcie@a0000000 { 90 pcie@a0000000 {
123 compatible = "xlnx,xdma-host-3.00" 91 compatible = "xlnx,xdma-host-3.00";
124 reg = <0x0 0xa0000000 0x0 0x100000 92 reg = <0x0 0xa0000000 0x0 0x10000000>;
125 ranges = <0x2000000 0x0 0xb0000000 93 ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
126 <0x43000000 0x5 0x0 0x5 0 94 <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
127 #address-cells = <3>; 95 #address-cells = <3>;
128 #size-cells = <2>; 96 #size-cells = <2>;
129 #interrupt-cells = <1>; 97 #interrupt-cells = <1>;
130 device_type = "pci"; 98 device_type = "pci";
131 interrupt-parent = <&gic>; 99 interrupt-parent = <&gic>;
132 interrupts = <GIC_SPI 89 IRQ_TYPE_ 100 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 91 IRQ_TYPE_ 101 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "misc", "msi0", 102 interrupt-names = "misc", "msi0", "msi1";
135 interrupt-map-mask = <0x0 0x0 0x0 103 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
136 interrupt-map = <0 0 0 1 &pcie_int 104 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
137 <0 0 0 2 &pcie_int 105 <0 0 0 2 &pcie_intc_0 1>,
138 <0 0 0 3 &pcie_int 106 <0 0 0 3 &pcie_intc_0 2>,
139 <0 0 0 4 &pcie_int 107 <0 0 0 4 &pcie_intc_0 3>;
140 pcie_intc_0: interrupt-controller 108 pcie_intc_0: interrupt-controller {
141 #address-cells = <0>; 109 #address-cells = <0>;
142 #interrupt-cells = <1>; 110 #interrupt-cells = <1>;
143 interrupt-controller; 111 interrupt-controller;
144 }; 112 };
145 }; 113 };
146 }; 114 };
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