1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/allwinn 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Allwinner A83t USB PHY !! 7 title: Allwinner A83t USB PHY Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Chen-Yu Tsai <wens@csie.org> 10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org> 11 - Maxime Ripard <mripard@kernel.org>
12 12
13 properties: 13 properties:
14 "#phy-cells": 14 "#phy-cells":
15 const: 1 15 const: 1
16 16
17 compatible: 17 compatible:
18 const: allwinner,sun8i-a83t-usb-phy 18 const: allwinner,sun8i-a83t-usb-phy
19 19
20 reg: 20 reg:
21 items: 21 items:
22 - description: PHY Control registers 22 - description: PHY Control registers
23 - description: PHY PMU1 registers 23 - description: PHY PMU1 registers
24 - description: PHY PMU2 registers 24 - description: PHY PMU2 registers
25 25
26 reg-names: 26 reg-names:
27 items: 27 items:
28 - const: phy_ctrl 28 - const: phy_ctrl
29 - const: pmu1 29 - const: pmu1
30 - const: pmu2 30 - const: pmu2
31 31
32 clocks: 32 clocks:
33 items: 33 items:
34 - description: USB OTG PHY bus clock 34 - description: USB OTG PHY bus clock
35 - description: USB Host 0 PHY bus clock 35 - description: USB Host 0 PHY bus clock
36 - description: USB Host 1 PHY bus clock 36 - description: USB Host 1 PHY bus clock
37 - description: USB HSIC 12MHz clock 37 - description: USB HSIC 12MHz clock
38 38
39 clock-names: 39 clock-names:
40 items: 40 items:
41 - const: usb0_phy 41 - const: usb0_phy
42 - const: usb1_phy 42 - const: usb1_phy
43 - const: usb2_phy 43 - const: usb2_phy
44 - const: usb2_hsic_12M 44 - const: usb2_hsic_12M
45 45
46 resets: 46 resets:
47 items: 47 items:
48 - description: USB OTG reset 48 - description: USB OTG reset
49 - description: USB Host 1 Controller res 49 - description: USB Host 1 Controller reset
50 - description: USB Host 2 Controller res 50 - description: USB Host 2 Controller reset
51 51
52 reset-names: 52 reset-names:
53 items: 53 items:
54 - const: usb0_reset 54 - const: usb0_reset
55 - const: usb1_reset 55 - const: usb1_reset
56 - const: usb2_reset 56 - const: usb2_reset
57 57
58 usb0_id_det-gpios: 58 usb0_id_det-gpios:
59 maxItems: 1 59 maxItems: 1
60 description: GPIO to the USB OTG ID pin 60 description: GPIO to the USB OTG ID pin
61 61
62 usb0_vbus_det-gpios: 62 usb0_vbus_det-gpios:
63 maxItems: 1 63 maxItems: 1
64 description: GPIO to the USB OTG VBUS dete 64 description: GPIO to the USB OTG VBUS detect pin
65 65
66 usb0_vbus_power-supply: 66 usb0_vbus_power-supply:
67 description: Power supply to detect the US 67 description: Power supply to detect the USB OTG VBUS
68 68
69 usb0_vbus-supply: 69 usb0_vbus-supply:
70 description: Regulator controlling USB OTG 70 description: Regulator controlling USB OTG VBUS
71 71
72 usb1_vbus-supply: 72 usb1_vbus-supply:
73 description: Regulator controlling USB1 Ho 73 description: Regulator controlling USB1 Host controller
74 74
75 usb2_vbus-supply: 75 usb2_vbus-supply:
76 description: Regulator controlling USB2 Ho 76 description: Regulator controlling USB2 Host controller
77 77
78 required: 78 required:
79 - "#phy-cells" 79 - "#phy-cells"
80 - compatible 80 - compatible
81 - clocks 81 - clocks
82 - clock-names 82 - clock-names
83 - reg 83 - reg
84 - reg-names 84 - reg-names
85 - resets 85 - resets
86 - reset-names 86 - reset-names
87 87
88 additionalProperties: false 88 additionalProperties: false
89 89
90 examples: 90 examples:
91 - | 91 - |
92 #include <dt-bindings/gpio/gpio.h> 92 #include <dt-bindings/gpio/gpio.h>
93 #include <dt-bindings/clock/sun8i-a83t-ccu 93 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
94 #include <dt-bindings/reset/sun8i-a83t-ccu 94 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
95 95
96 phy@1c19400 { 96 phy@1c19400 {
97 #phy-cells = <1>; 97 #phy-cells = <1>;
98 compatible = "allwinner,sun8i-a83t-usb 98 compatible = "allwinner,sun8i-a83t-usb-phy";
99 reg = <0x01c19400 0x10>, 99 reg = <0x01c19400 0x10>,
100 <0x01c1a800 0x14>, 100 <0x01c1a800 0x14>,
101 <0x01c1b800 0x14>; 101 <0x01c1b800 0x14>;
102 reg-names = "phy_ctrl", 102 reg-names = "phy_ctrl",
103 "pmu1", 103 "pmu1",
104 "pmu2"; 104 "pmu2";
105 clocks = <&ccu CLK_USB_PHY0>, 105 clocks = <&ccu CLK_USB_PHY0>,
106 <&ccu CLK_USB_PHY1>, 106 <&ccu CLK_USB_PHY1>,
107 <&ccu CLK_USB_HSIC>, 107 <&ccu CLK_USB_HSIC>,
108 <&ccu CLK_USB_HSIC_12M>; 108 <&ccu CLK_USB_HSIC_12M>;
109 clock-names = "usb0_phy", 109 clock-names = "usb0_phy",
110 "usb1_phy", 110 "usb1_phy",
111 "usb2_phy", 111 "usb2_phy",
112 "usb2_hsic_12M"; 112 "usb2_hsic_12M";
113 resets = <&ccu RST_USB_PHY0>, 113 resets = <&ccu RST_USB_PHY0>,
114 <&ccu RST_USB_PHY1>, 114 <&ccu RST_USB_PHY1>,
115 <&ccu RST_USB_HSIC>; 115 <&ccu RST_USB_HSIC>;
116 reset-names = "usb0_reset", 116 reset-names = "usb0_reset",
117 "usb1_reset", 117 "usb1_reset",
118 "usb2_reset"; 118 "usb2_reset";
119 usb0_id_det-gpios = <&pio 7 11 GPIO_AC 119 usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
120 usb0_vbus_power-supply = <&usb_power_s 120 usb0_vbus_power-supply = <&usb_power_supply>;
121 usb0_vbus-supply = <®_drivevbus>; 121 usb0_vbus-supply = <®_drivevbus>;
122 usb1_vbus-supply = <®_usb1_vbus>; 122 usb1_vbus-supply = <®_usb1_vbus>;
123 usb2_vbus-supply = <®_usb2_vbus>; 123 usb2_vbus-supply = <®_usb2_vbus>;
124 }; 124 };
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