1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Freescale i.MX8QM SoC series High Speed
8
9 maintainers:
10 - Richard Zhu <hongxing.zhu@nxp.com>
11
12 properties:
13 compatible:
14 enum:
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
17 reg:
18 items:
19 - description: Base address and length o
20 - description: HSIO control and status r
21 - description: HSIO CSR of the controlle
22 - description: HSIO CSR for MISC
23
24 reg-names:
25 items:
26 - const: reg
27 - const: phy
28 - const: ctrl
29 - const: misc
30
31 "#phy-cells":
32 const: 3
33 description:
34 The first defines lane index.
35 The second defines the type of the PHY r
36 The third defines the controller index,
37 is bound to the lane.
38
39 clocks:
40 minItems: 5
41 maxItems: 14
42
43 clock-names:
44 minItems: 5
45 maxItems: 14
46
47 fsl,hsio-cfg:
48 description: |
49 Specifies the use case of the HSIO modul
50 Regarding the design of i.MX8QM HSIO sub
51 confiured as following three use cases.
52 +---------------------------------------
53 | | i.MX8QM
54 |------------------|--------------------
55 | | Lane0| Lane1| Lane2
56 |------------------|------|------|------
57 | pciea-x2-sata | PCIEA| PCIEA| SATA
58 |------------------|------|------|------
59 | pciea-x2-pcieb | PCIEA| PCIEA| PCIEB
60 |------------------|------|------|------
61 | pciea-pcieb-sata | PCIEA| PCIEB| SATA
62 +---------------------------------------
63 $ref: /schemas/types.yaml#/definitions/str
64 enum: [ pciea-x2-sata, pciea-x2-pcieb, pci
65 default: pciea-pcieb-sata
66
67 fsl,refclk-pad-mode:
68 description:
69 Specifies the mode of the refclk pad use
70 provided externally via the refclk pad)
71 derived from SoC internal source and pro
72 This property not exists means unused(PH
73 SoC internal source).
74 $ref: /schemas/types.yaml#/definitions/str
75 enum: [ input, output, unused ]
76 default: unused
77
78 power-domains:
79 minItems: 1
80 maxItems: 2
81
82 required:
83 - compatible
84 - reg
85 - reg-names
86 - "#phy-cells"
87 - clocks
88 - clock-names
89 - fsl,hsio-cfg
90
91 allOf:
92 - if:
93 properties:
94 compatible:
95 contains:
96 enum:
97 - fsl,imx8qxp-hsio
98 then:
99 properties:
100 clock-names:
101 items:
102 - const: pclk0
103 - const: apb_pclk0
104 - const: phy0_crr
105 - const: ctl0_crr
106 - const: misc_crr
107 power-domains:
108 maxItems: 1
109
110 - if:
111 properties:
112 compatible:
113 contains:
114 enum:
115 - fsl,imx8qm-hsio
116 then:
117 properties:
118 clock-names:
119 items:
120 - const: pclk0
121 - const: pclk1
122 - const: apb_pclk0
123 - const: apb_pclk1
124 - const: pclk2
125 - const: epcs_tx
126 - const: epcs_rx
127 - const: apb_pclk2
128 - const: phy0_crr
129 - const: phy1_crr
130 - const: ctl0_crr
131 - const: ctl1_crr
132 - const: ctl2_crr
133 - const: misc_crr
134 power-domains:
135 minItems: 2
136
137 additionalProperties: false
138
139 examples:
140 - |
141 #include <dt-bindings/clock/imx8-clock.h>
142 #include <dt-bindings/clock/imx8-lpcg.h>
143 #include <dt-bindings/firmware/imx/rsrc.h>
144 #include <dt-bindings/phy/phy-imx8-pcie.h>
145
146 phy@5f1a0000 {
147 compatible = "fsl,imx8qxp-hsio";
148 reg = <0x5f1a0000 0x10000>,
149 <0x5f120000 0x10000>,
150 <0x5f140000 0x10000>,
151 <0x5f160000 0x10000>;
152 reg-names = "reg", "phy", "ctrl", "mis
153 clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
154 <&phyx1_lpcg IMX_LPCG_CLK_4>,
155 <&phyx1_crr1_lpcg IMX_LPCG_CL
156 <&pcieb_crr3_lpcg IMX_LPCG_CL
157 <&misc_crr5_lpcg IMX_LPCG_CLK
158 clock-names = "pclk0", "apb_pclk0", "p
159 power-domains = <&pd IMX_SC_R_SERDES_1
160 #phy-cells = <3>;
161 fsl,hsio-cfg = "pciea-pcieb-sata";
162 fsl,refclk-pad-mode = "input";
163 };
164 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.