1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek 2 # Copyright (c) 2020 MediaTek
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/mediate 5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: MediaTek MIPI Display Serial Interface !! 8 title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
9 9
10 maintainers: 10 maintainers:
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de> 12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com> 13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 14
15 description: The MIPI DSI PHY supports up to 4 15 description: The MIPI DSI PHY supports up to 4-lane output.
16 16
17 properties: 17 properties:
18 $nodename: 18 $nodename:
19 pattern: "^dsi-phy@[0-9a-f]+$" 19 pattern: "^dsi-phy@[0-9a-f]+$"
20 20
21 compatible: 21 compatible:
22 oneOf: 22 oneOf:
23 - items: 23 - items:
24 - enum: 24 - enum:
25 - mediatek,mt7623-mipi-tx 25 - mediatek,mt7623-mipi-tx
26 - const: mediatek,mt2701-mipi-tx 26 - const: mediatek,mt2701-mipi-tx
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - mediatek,mt6795-mipi-tx <<
30 - const: mediatek,mt8173-mipi-tx <<
31 - items: <<
32 - enum: <<
33 - mediatek,mt8188-mipi-tx <<
34 - mediatek,mt8195-mipi-tx <<
35 - mediatek,mt8365-mipi-tx 29 - mediatek,mt8365-mipi-tx
36 - const: mediatek,mt8183-mipi-tx 30 - const: mediatek,mt8183-mipi-tx
37 - const: mediatek,mt2701-mipi-tx 31 - const: mediatek,mt2701-mipi-tx
38 - const: mediatek,mt8173-mipi-tx 32 - const: mediatek,mt8173-mipi-tx
39 - const: mediatek,mt8183-mipi-tx 33 - const: mediatek,mt8183-mipi-tx
40 34
41 reg: 35 reg:
42 maxItems: 1 36 maxItems: 1
43 37
44 clocks: 38 clocks:
45 items: 39 items:
46 - description: PLL reference clock 40 - description: PLL reference clock
47 41
48 clock-output-names: 42 clock-output-names:
49 maxItems: 1 43 maxItems: 1
50 44
51 "#phy-cells": 45 "#phy-cells":
52 const: 0 46 const: 0
53 47
54 "#clock-cells": 48 "#clock-cells":
55 const: 0 49 const: 0
56 50
57 nvmem-cells: 51 nvmem-cells:
58 maxItems: 1 52 maxItems: 1
59 description: A phandle to the calibration 53 description: A phandle to the calibration data provided by a nvmem device,
60 if unspecified, default values shall be 54 if unspecified, default values shall be used.
61 55
62 nvmem-cell-names: 56 nvmem-cell-names:
63 items: 57 items:
64 - const: calibration-data 58 - const: calibration-data
65 59
66 drive-strength-microamp: 60 drive-strength-microamp:
67 description: adjust driving current 61 description: adjust driving current
68 multipleOf: 200 62 multipleOf: 200
69 minimum: 2000 63 minimum: 2000
70 maximum: 6000 64 maximum: 6000
71 default: 4600 65 default: 4600
72 66
73 required: 67 required:
74 - compatible 68 - compatible
75 - reg 69 - reg
76 - clocks 70 - clocks
77 - clock-output-names 71 - clock-output-names
78 - "#phy-cells" 72 - "#phy-cells"
79 - "#clock-cells" 73 - "#clock-cells"
80 74
81 additionalProperties: false 75 additionalProperties: false
82 76
83 examples: 77 examples:
84 - | 78 - |
85 #include <dt-bindings/clock/mt8173-clk.h> 79 #include <dt-bindings/clock/mt8173-clk.h>
86 dsi-phy@10215000 { 80 dsi-phy@10215000 {
87 compatible = "mediatek,mt8173-mipi-tx" 81 compatible = "mediatek,mt8173-mipi-tx";
88 reg = <0x10215000 0x1000>; 82 reg = <0x10215000 0x1000>;
89 clocks = <&clk26m>; 83 clocks = <&clk26m>;
90 clock-output-names = "mipi_tx0_pll"; 84 clock-output-names = "mipi_tx0_pll";
91 drive-strength-microamp = <4000>; 85 drive-strength-microamp = <4000>;
92 nvmem-cells = <&mipi_tx_calibration>; !! 86 nvmem-cells= <&mipi_tx_calibration>;
93 nvmem-cell-names = "calibration-data"; 87 nvmem-cell-names = "calibration-data";
94 #clock-cells = <0>; 88 #clock-cells = <0>;
95 #phy-cells = <0>; 89 #phy-cells = <0>;
96 }; 90 };
97 91
98 ... 92 ...
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