1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek 2 # Copyright (c) 2020 MediaTek
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/phy/mediate 5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: MediaTek MIPI Display Serial Interface 8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
9 9
10 maintainers: 10 maintainers:
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de> 12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com> 13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 14
15 description: The MIPI DSI PHY supports up to 4 15 description: The MIPI DSI PHY supports up to 4-lane output.
16 16
17 properties: 17 properties:
18 $nodename: 18 $nodename:
19 pattern: "^dsi-phy@[0-9a-f]+$" 19 pattern: "^dsi-phy@[0-9a-f]+$"
20 20
21 compatible: 21 compatible:
22 oneOf: 22 oneOf:
23 - items: 23 - items:
24 - enum: 24 - enum:
25 - mediatek,mt7623-mipi-tx 25 - mediatek,mt7623-mipi-tx
26 - const: mediatek,mt2701-mipi-tx 26 - const: mediatek,mt2701-mipi-tx
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - mediatek,mt6795-mipi-tx 29 - mediatek,mt6795-mipi-tx
30 - const: mediatek,mt8173-mipi-tx 30 - const: mediatek,mt8173-mipi-tx
31 - items: 31 - items:
32 - enum: 32 - enum:
33 - mediatek,mt8188-mipi-tx <<
34 - mediatek,mt8195-mipi-tx <<
35 - mediatek,mt8365-mipi-tx 33 - mediatek,mt8365-mipi-tx
36 - const: mediatek,mt8183-mipi-tx 34 - const: mediatek,mt8183-mipi-tx
37 - const: mediatek,mt2701-mipi-tx 35 - const: mediatek,mt2701-mipi-tx
38 - const: mediatek,mt8173-mipi-tx 36 - const: mediatek,mt8173-mipi-tx
39 - const: mediatek,mt8183-mipi-tx 37 - const: mediatek,mt8183-mipi-tx
40 38
41 reg: 39 reg:
42 maxItems: 1 40 maxItems: 1
43 41
44 clocks: 42 clocks:
45 items: 43 items:
46 - description: PLL reference clock 44 - description: PLL reference clock
47 45
48 clock-output-names: 46 clock-output-names:
49 maxItems: 1 47 maxItems: 1
50 48
51 "#phy-cells": 49 "#phy-cells":
52 const: 0 50 const: 0
53 51
54 "#clock-cells": 52 "#clock-cells":
55 const: 0 53 const: 0
56 54
57 nvmem-cells: 55 nvmem-cells:
58 maxItems: 1 56 maxItems: 1
59 description: A phandle to the calibration 57 description: A phandle to the calibration data provided by a nvmem device,
60 if unspecified, default values shall be 58 if unspecified, default values shall be used.
61 59
62 nvmem-cell-names: 60 nvmem-cell-names:
63 items: 61 items:
64 - const: calibration-data 62 - const: calibration-data
65 63
66 drive-strength-microamp: 64 drive-strength-microamp:
67 description: adjust driving current 65 description: adjust driving current
68 multipleOf: 200 66 multipleOf: 200
69 minimum: 2000 67 minimum: 2000
70 maximum: 6000 68 maximum: 6000
71 default: 4600 69 default: 4600
72 70
73 required: 71 required:
74 - compatible 72 - compatible
75 - reg 73 - reg
76 - clocks 74 - clocks
77 - clock-output-names 75 - clock-output-names
78 - "#phy-cells" 76 - "#phy-cells"
79 - "#clock-cells" 77 - "#clock-cells"
80 78
81 additionalProperties: false 79 additionalProperties: false
82 80
83 examples: 81 examples:
84 - | 82 - |
85 #include <dt-bindings/clock/mt8173-clk.h> 83 #include <dt-bindings/clock/mt8173-clk.h>
86 dsi-phy@10215000 { 84 dsi-phy@10215000 {
87 compatible = "mediatek,mt8173-mipi-tx" 85 compatible = "mediatek,mt8173-mipi-tx";
88 reg = <0x10215000 0x1000>; 86 reg = <0x10215000 0x1000>;
89 clocks = <&clk26m>; 87 clocks = <&clk26m>;
90 clock-output-names = "mipi_tx0_pll"; 88 clock-output-names = "mipi_tx0_pll";
91 drive-strength-microamp = <4000>; 89 drive-strength-microamp = <4000>;
92 nvmem-cells = <&mipi_tx_calibration>; 90 nvmem-cells = <&mipi_tx_calibration>;
93 nvmem-cell-names = "calibration-data"; 91 nvmem-cell-names = "calibration-data";
94 #clock-cells = <0>; 92 #clock-cells = <0>;
95 #phy-cells = <0>; 93 #phy-cells = <0>;
96 }; 94 };
97 95
98 ... 96 ...
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