1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cad !! 4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: http://devicetree.org/meta-schemas/co !! 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
6 6
7 title: Cadence Torrent SD0801 PHY !! 7 title: Cadence Torrent SD0801 PHY binding
8 8
9 description: 9 description:
10 This binding describes the Cadence SD0801 PH 10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP Disp 11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol co 12 PHY also supports multilink multiprotocol combinations including protocols
13 such as PCIe, USB, SGMII, QSGMII etc. 13 such as PCIe, USB, SGMII, QSGMII etc.
14 14
15 maintainers: 15 maintainers:
16 - Swapnil Jakhade <sjakhade@cadence.com> 16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com>
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 enum: 21 enum:
22 - cdns,torrent-phy 22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g <<
24 - ti,j721e-serdes-10g 23 - ti,j721e-serdes-10g
25 24
26 '#address-cells': 25 '#address-cells':
27 const: 1 26 const: 1
28 27
29 '#size-cells': 28 '#size-cells':
30 const: 0 29 const: 0
31 30
32 '#clock-cells': 31 '#clock-cells':
33 const: 1 32 const: 1
34 33
35 clocks: 34 clocks:
36 minItems: 1 35 minItems: 1
37 maxItems: 2 36 maxItems: 2
38 description: 37 description:
39 PHY input reference clocks - refclk (for !! 38 PHY reference clock for 1 item. Must contain an entry in clock-names.
40 pll1_refclk is optional and used for mul !! 39 Optional Parent to enable output reference clock.
41 separate reference clock for each protoc <<
42 Same refclk is used for both PLL0 and PL <<
43 Optional parent clock (phy_en_refclk) to <<
44 on some platforms to output either deriv <<
45 40
46 clock-names: 41 clock-names:
47 minItems: 1 42 minItems: 1
48 items: 43 items:
49 - const: refclk 44 - const: refclk
50 - enum: [ pll1_refclk, phy_en_refclk ] !! 45 - const: phy_en_refclk
>> 46
>> 47 assigned-clocks:
>> 48 maxItems: 3
>> 49
>> 50 assigned-clock-parents:
>> 51 maxItems: 3
51 52
52 reg: 53 reg:
53 minItems: 1 54 minItems: 1
54 items: 55 items:
55 - description: Offset of the Torrent PHY 56 - description: Offset of the Torrent PHY configuration registers.
56 - description: Offset of the DPTX PHY co 57 - description: Offset of the DPTX PHY configuration registers.
57 58
58 reg-names: 59 reg-names:
59 minItems: 1 60 minItems: 1
60 items: 61 items:
61 - const: torrent_phy 62 - const: torrent_phy
62 - const: dptx_phy 63 - const: dptx_phy
63 64
64 resets: 65 resets:
65 minItems: 1 66 minItems: 1
66 items: 67 items:
67 - description: Torrent PHY reset. 68 - description: Torrent PHY reset.
68 - description: Torrent APB reset. This i 69 - description: Torrent APB reset. This is optional.
69 70
70 reset-names: 71 reset-names:
71 minItems: 1 72 minItems: 1
72 items: 73 items:
73 - const: torrent_reset 74 - const: torrent_reset
74 - const: torrent_apb 75 - const: torrent_apb
75 76
76 patternProperties: 77 patternProperties:
77 '^phy@[0-3]$': 78 '^phy@[0-3]$':
78 type: object 79 type: object
79 description: 80 description:
80 Each group of PHY lanes with a single ma 81 Each group of PHY lanes with a single master lane should be represented as a sub-node.
81 properties: 82 properties:
82 reg: 83 reg:
83 description: 84 description:
84 The master lane number. This is the 85 The master lane number. This is the lowest numbered lane in the lane group.
85 minimum: 0 86 minimum: 0
86 maximum: 3 87 maximum: 3
87 88
88 resets: 89 resets:
89 minItems: 1 90 minItems: 1
90 maxItems: 4 91 maxItems: 4
91 description: 92 description:
92 Contains list of resets, one per lan 93 Contains list of resets, one per lane, to get all the link lanes out of reset.
93 94
94 "#phy-cells": 95 "#phy-cells":
95 const: 0 96 const: 0
96 97
97 cdns,phy-type: 98 cdns,phy-type:
98 description: 99 description:
99 Specifies the type of PHY for which 100 Specifies the type of PHY for which the group of PHY lanes is used.
100 Refer include/dt-bindings/phy/phy.h. 101 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
101 $ref: /schemas/types.yaml#/definitions 102 $ref: /schemas/types.yaml#/definitions/uint32
102 minimum: 1 103 minimum: 1
103 maximum: 9 104 maximum: 9
104 105
105 cdns,num-lanes: 106 cdns,num-lanes:
106 description: 107 description:
107 Number of lanes. 108 Number of lanes.
108 $ref: /schemas/types.yaml#/definitions 109 $ref: /schemas/types.yaml#/definitions/uint32
109 enum: [1, 2, 3, 4] 110 enum: [1, 2, 3, 4]
110 default: 4 111 default: 4
111 112
112 cdns,ssc-mode: 113 cdns,ssc-mode:
113 description: 114 description:
114 Specifies the Spread Spectrum Clocki 115 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
115 EXTERNAL_SSC or INTERNAL_SSC. 116 EXTERNAL_SSC or INTERNAL_SSC.
116 Refer include/dt-bindings/phy/phy-ca 117 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
117 $ref: /schemas/types.yaml#/definitions 118 $ref: /schemas/types.yaml#/definitions/uint32
118 enum: [0, 1, 2] 119 enum: [0, 1, 2]
119 default: 0 120 default: 0
120 121
121 cdns,max-bit-rate: 122 cdns,max-bit-rate:
122 description: 123 description:
123 Maximum DisplayPort link bit rate to 124 Maximum DisplayPort link bit rate to use, in Mbps
124 $ref: /schemas/types.yaml#/definitions 125 $ref: /schemas/types.yaml#/definitions/uint32
125 enum: [2160, 2430, 2700, 3240, 4320, 5 126 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
126 default: 8100 127 default: 8100
127 128
128 required: 129 required:
129 - reg 130 - reg
130 - resets 131 - resets
131 - "#phy-cells" 132 - "#phy-cells"
132 - cdns,phy-type 133 - cdns,phy-type
133 - cdns,num-lanes 134 - cdns,num-lanes
134 135
135 additionalProperties: false 136 additionalProperties: false
136 137
137 required: 138 required:
138 - compatible 139 - compatible
139 - "#address-cells" 140 - "#address-cells"
140 - "#size-cells" 141 - "#size-cells"
141 - clocks 142 - clocks
142 - clock-names 143 - clock-names
143 - reg 144 - reg
144 - reg-names 145 - reg-names
145 - resets 146 - resets
146 - reset-names 147 - reset-names
147 148
148 additionalProperties: false 149 additionalProperties: false
149 150
150 examples: 151 examples:
151 - | 152 - |
152 #include <dt-bindings/phy/phy.h> 153 #include <dt-bindings/phy/phy.h>
153 154
154 bus { 155 bus {
155 #address-cells = <2>; 156 #address-cells = <2>;
156 #size-cells = <2>; 157 #size-cells = <2>;
157 158
158 torrent-phy@f0fb500000 { 159 torrent-phy@f0fb500000 {
159 compatible = "cdns,torrent-phy"; 160 compatible = "cdns,torrent-phy";
160 reg = <0xf0 0xfb500000 0x0 0x00100 161 reg = <0xf0 0xfb500000 0x0 0x00100000>,
161 <0xf0 0xfb030a00 0x0 0x00000 162 <0xf0 0xfb030a00 0x0 0x00000040>;
162 reg-names = "torrent_phy", "dptx_p 163 reg-names = "torrent_phy", "dptx_phy";
163 resets = <&phyrst 0>; 164 resets = <&phyrst 0>;
164 reset-names = "torrent_reset"; 165 reset-names = "torrent_reset";
165 clocks = <&ref_clk>; 166 clocks = <&ref_clk>;
166 clock-names = "refclk"; 167 clock-names = "refclk";
167 #address-cells = <1>; 168 #address-cells = <1>;
168 #size-cells = <0>; 169 #size-cells = <0>;
169 phy@0 { 170 phy@0 {
170 reg = <0>; 171 reg = <0>;
171 resets = <&phyrst 1>, <&phyrst 172 resets = <&phyrst 1>, <&phyrst 2>,
172 <&phyrst 3>, <&phyrst 173 <&phyrst 3>, <&phyrst 4>;
173 #phy-cells = <0>; 174 #phy-cells = <0>;
174 cdns,phy-type = <PHY_TYPE_DP>; 175 cdns,phy-type = <PHY_TYPE_DP>;
175 cdns,num-lanes = <4>; 176 cdns,num-lanes = <4>;
176 cdns,max-bit-rate = <8100>; 177 cdns,max-bit-rate = <8100>;
177 }; 178 };
178 }; 179 };
179 }; 180 };
180 - | 181 - |
181 #include <dt-bindings/phy/phy.h> 182 #include <dt-bindings/phy/phy.h>
182 #include <dt-bindings/phy/phy-cadence.h> 183 #include <dt-bindings/phy/phy-cadence.h>
183 184
184 bus { 185 bus {
185 #address-cells = <2>; 186 #address-cells = <2>;
186 #size-cells = <2>; 187 #size-cells = <2>;
187 188
188 torrent-phy@f0fb500000 { 189 torrent-phy@f0fb500000 {
189 compatible = "cdns,torrent-phy"; 190 compatible = "cdns,torrent-phy";
190 reg = <0xf0 0xfb500000 0x0 0x00100 191 reg = <0xf0 0xfb500000 0x0 0x00100000>;
191 reg-names = "torrent_phy"; 192 reg-names = "torrent_phy";
192 resets = <&phyrst 0>, <&phyrst 1>; 193 resets = <&phyrst 0>, <&phyrst 1>;
193 reset-names = "torrent_reset", "to 194 reset-names = "torrent_reset", "torrent_apb";
194 clocks = <&ref_clk>; 195 clocks = <&ref_clk>;
195 clock-names = "refclk"; 196 clock-names = "refclk";
196 #address-cells = <1>; 197 #address-cells = <1>;
197 #size-cells = <0>; 198 #size-cells = <0>;
198 phy@0 { 199 phy@0 {
199 reg = <0>; 200 reg = <0>;
200 resets = <&phyrst 2>, <&phyrst 201 resets = <&phyrst 2>, <&phyrst 3>;
201 #phy-cells = <0>; 202 #phy-cells = <0>;
202 cdns,phy-type = <PHY_TYPE_PCIE 203 cdns,phy-type = <PHY_TYPE_PCIE>;
203 cdns,num-lanes = <2>; 204 cdns,num-lanes = <2>;
204 cdns,ssc-mode = <CDNS_SERDES_N !! 205 cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;
205 }; 206 };
206 207
207 phy@2 { 208 phy@2 {
208 reg = <2>; 209 reg = <2>;
209 resets = <&phyrst 4>; 210 resets = <&phyrst 4>;
210 #phy-cells = <0>; 211 #phy-cells = <0>;
211 cdns,phy-type = <PHY_TYPE_SGMI 212 cdns,phy-type = <PHY_TYPE_SGMII>;
212 cdns,num-lanes = <1>; 213 cdns,num-lanes = <1>;
213 cdns,ssc-mode = <CDNS_SERDES_N !! 214 cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;
214 }; 215 };
215 }; 216 };
216 }; 217 };
217 ... 218 ...
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