1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cad 4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Cadence Torrent SD0801 PHY 7 title: Cadence Torrent SD0801 PHY
8 8
9 description: 9 description:
10 This binding describes the Cadence SD0801 PH 10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP Disp 11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol co 12 PHY also supports multilink multiprotocol combinations including protocols
13 such as PCIe, USB, SGMII, QSGMII etc. 13 such as PCIe, USB, SGMII, QSGMII etc.
14 14
15 maintainers: 15 maintainers:
16 - Swapnil Jakhade <sjakhade@cadence.com> 16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com>
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 enum: 21 enum:
22 - cdns,torrent-phy 22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g <<
24 - ti,j721e-serdes-10g 23 - ti,j721e-serdes-10g
25 24
26 '#address-cells': 25 '#address-cells':
27 const: 1 26 const: 1
28 27
29 '#size-cells': 28 '#size-cells':
30 const: 0 29 const: 0
31 30
32 '#clock-cells': 31 '#clock-cells':
33 const: 1 32 const: 1
34 33
35 clocks: 34 clocks:
36 minItems: 1 35 minItems: 1
37 maxItems: 2 36 maxItems: 2
38 description: 37 description:
39 PHY input reference clocks - refclk (for !! 38 PHY reference clock for 1 item. Must contain an entry in clock-names.
40 pll1_refclk is optional and used for mul !! 39 Optional Parent to enable output reference clock.
41 separate reference clock for each protoc <<
42 Same refclk is used for both PLL0 and PL <<
43 Optional parent clock (phy_en_refclk) to <<
44 on some platforms to output either deriv <<
45 40
46 clock-names: 41 clock-names:
47 minItems: 1 42 minItems: 1
48 items: 43 items:
49 - const: refclk 44 - const: refclk
50 - enum: [ pll1_refclk, phy_en_refclk ] !! 45 - const: phy_en_refclk
51 46
52 reg: 47 reg:
53 minItems: 1 48 minItems: 1
54 items: 49 items:
55 - description: Offset of the Torrent PHY 50 - description: Offset of the Torrent PHY configuration registers.
56 - description: Offset of the DPTX PHY co 51 - description: Offset of the DPTX PHY configuration registers.
57 52
58 reg-names: 53 reg-names:
59 minItems: 1 54 minItems: 1
60 items: 55 items:
61 - const: torrent_phy 56 - const: torrent_phy
62 - const: dptx_phy 57 - const: dptx_phy
63 58
64 resets: 59 resets:
65 minItems: 1 60 minItems: 1
66 items: 61 items:
67 - description: Torrent PHY reset. 62 - description: Torrent PHY reset.
68 - description: Torrent APB reset. This i 63 - description: Torrent APB reset. This is optional.
69 64
70 reset-names: 65 reset-names:
71 minItems: 1 66 minItems: 1
72 items: 67 items:
73 - const: torrent_reset 68 - const: torrent_reset
74 - const: torrent_apb 69 - const: torrent_apb
75 70
76 patternProperties: 71 patternProperties:
77 '^phy@[0-3]$': 72 '^phy@[0-3]$':
78 type: object 73 type: object
79 description: 74 description:
80 Each group of PHY lanes with a single ma 75 Each group of PHY lanes with a single master lane should be represented as a sub-node.
81 properties: 76 properties:
82 reg: 77 reg:
83 description: 78 description:
84 The master lane number. This is the 79 The master lane number. This is the lowest numbered lane in the lane group.
85 minimum: 0 80 minimum: 0
86 maximum: 3 81 maximum: 3
87 82
88 resets: 83 resets:
89 minItems: 1 84 minItems: 1
90 maxItems: 4 85 maxItems: 4
91 description: 86 description:
92 Contains list of resets, one per lan 87 Contains list of resets, one per lane, to get all the link lanes out of reset.
93 88
94 "#phy-cells": 89 "#phy-cells":
95 const: 0 90 const: 0
96 91
97 cdns,phy-type: 92 cdns,phy-type:
98 description: 93 description:
99 Specifies the type of PHY for which 94 Specifies the type of PHY for which the group of PHY lanes is used.
100 Refer include/dt-bindings/phy/phy.h. 95 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
101 $ref: /schemas/types.yaml#/definitions 96 $ref: /schemas/types.yaml#/definitions/uint32
102 minimum: 1 97 minimum: 1
103 maximum: 9 98 maximum: 9
104 99
105 cdns,num-lanes: 100 cdns,num-lanes:
106 description: 101 description:
107 Number of lanes. 102 Number of lanes.
108 $ref: /schemas/types.yaml#/definitions 103 $ref: /schemas/types.yaml#/definitions/uint32
109 enum: [1, 2, 3, 4] 104 enum: [1, 2, 3, 4]
110 default: 4 105 default: 4
111 106
112 cdns,ssc-mode: 107 cdns,ssc-mode:
113 description: 108 description:
114 Specifies the Spread Spectrum Clocki 109 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
115 EXTERNAL_SSC or INTERNAL_SSC. 110 EXTERNAL_SSC or INTERNAL_SSC.
116 Refer include/dt-bindings/phy/phy-ca 111 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
117 $ref: /schemas/types.yaml#/definitions 112 $ref: /schemas/types.yaml#/definitions/uint32
118 enum: [0, 1, 2] 113 enum: [0, 1, 2]
119 default: 0 114 default: 0
120 115
121 cdns,max-bit-rate: 116 cdns,max-bit-rate:
122 description: 117 description:
123 Maximum DisplayPort link bit rate to 118 Maximum DisplayPort link bit rate to use, in Mbps
124 $ref: /schemas/types.yaml#/definitions 119 $ref: /schemas/types.yaml#/definitions/uint32
125 enum: [2160, 2430, 2700, 3240, 4320, 5 120 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
126 default: 8100 121 default: 8100
127 122
128 required: 123 required:
129 - reg 124 - reg
130 - resets 125 - resets
131 - "#phy-cells" 126 - "#phy-cells"
132 - cdns,phy-type 127 - cdns,phy-type
133 - cdns,num-lanes 128 - cdns,num-lanes
134 129
135 additionalProperties: false 130 additionalProperties: false
136 131
137 required: 132 required:
138 - compatible 133 - compatible
139 - "#address-cells" 134 - "#address-cells"
140 - "#size-cells" 135 - "#size-cells"
141 - clocks 136 - clocks
142 - clock-names 137 - clock-names
143 - reg 138 - reg
144 - reg-names 139 - reg-names
145 - resets 140 - resets
146 - reset-names 141 - reset-names
147 142
148 additionalProperties: false 143 additionalProperties: false
149 144
150 examples: 145 examples:
151 - | 146 - |
152 #include <dt-bindings/phy/phy.h> 147 #include <dt-bindings/phy/phy.h>
153 148
154 bus { 149 bus {
155 #address-cells = <2>; 150 #address-cells = <2>;
156 #size-cells = <2>; 151 #size-cells = <2>;
157 152
158 torrent-phy@f0fb500000 { 153 torrent-phy@f0fb500000 {
159 compatible = "cdns,torrent-phy"; 154 compatible = "cdns,torrent-phy";
160 reg = <0xf0 0xfb500000 0x0 0x00100 155 reg = <0xf0 0xfb500000 0x0 0x00100000>,
161 <0xf0 0xfb030a00 0x0 0x00000 156 <0xf0 0xfb030a00 0x0 0x00000040>;
162 reg-names = "torrent_phy", "dptx_p 157 reg-names = "torrent_phy", "dptx_phy";
163 resets = <&phyrst 0>; 158 resets = <&phyrst 0>;
164 reset-names = "torrent_reset"; 159 reset-names = "torrent_reset";
165 clocks = <&ref_clk>; 160 clocks = <&ref_clk>;
166 clock-names = "refclk"; 161 clock-names = "refclk";
167 #address-cells = <1>; 162 #address-cells = <1>;
168 #size-cells = <0>; 163 #size-cells = <0>;
169 phy@0 { 164 phy@0 {
170 reg = <0>; 165 reg = <0>;
171 resets = <&phyrst 1>, <&phyrst 166 resets = <&phyrst 1>, <&phyrst 2>,
172 <&phyrst 3>, <&phyrst 167 <&phyrst 3>, <&phyrst 4>;
173 #phy-cells = <0>; 168 #phy-cells = <0>;
174 cdns,phy-type = <PHY_TYPE_DP>; 169 cdns,phy-type = <PHY_TYPE_DP>;
175 cdns,num-lanes = <4>; 170 cdns,num-lanes = <4>;
176 cdns,max-bit-rate = <8100>; 171 cdns,max-bit-rate = <8100>;
177 }; 172 };
178 }; 173 };
179 }; 174 };
180 - | 175 - |
181 #include <dt-bindings/phy/phy.h> 176 #include <dt-bindings/phy/phy.h>
182 #include <dt-bindings/phy/phy-cadence.h> 177 #include <dt-bindings/phy/phy-cadence.h>
183 178
184 bus { 179 bus {
185 #address-cells = <2>; 180 #address-cells = <2>;
186 #size-cells = <2>; 181 #size-cells = <2>;
187 182
188 torrent-phy@f0fb500000 { 183 torrent-phy@f0fb500000 {
189 compatible = "cdns,torrent-phy"; 184 compatible = "cdns,torrent-phy";
190 reg = <0xf0 0xfb500000 0x0 0x00100 185 reg = <0xf0 0xfb500000 0x0 0x00100000>;
191 reg-names = "torrent_phy"; 186 reg-names = "torrent_phy";
192 resets = <&phyrst 0>, <&phyrst 1>; 187 resets = <&phyrst 0>, <&phyrst 1>;
193 reset-names = "torrent_reset", "to 188 reset-names = "torrent_reset", "torrent_apb";
194 clocks = <&ref_clk>; 189 clocks = <&ref_clk>;
195 clock-names = "refclk"; 190 clock-names = "refclk";
196 #address-cells = <1>; 191 #address-cells = <1>;
197 #size-cells = <0>; 192 #size-cells = <0>;
198 phy@0 { 193 phy@0 {
199 reg = <0>; 194 reg = <0>;
200 resets = <&phyrst 2>, <&phyrst 195 resets = <&phyrst 2>, <&phyrst 3>;
201 #phy-cells = <0>; 196 #phy-cells = <0>;
202 cdns,phy-type = <PHY_TYPE_PCIE 197 cdns,phy-type = <PHY_TYPE_PCIE>;
203 cdns,num-lanes = <2>; 198 cdns,num-lanes = <2>;
204 cdns,ssc-mode = <CDNS_SERDES_N 199 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
205 }; 200 };
206 201
207 phy@2 { 202 phy@2 {
208 reg = <2>; 203 reg = <2>;
209 resets = <&phyrst 4>; 204 resets = <&phyrst 4>;
210 #phy-cells = <0>; 205 #phy-cells = <0>;
211 cdns,phy-type = <PHY_TYPE_SGMI 206 cdns,phy-type = <PHY_TYPE_SGMII>;
212 cdns,num-lanes = <1>; 207 cdns,num-lanes = <1>;
213 cdns,ssc-mode = <CDNS_SERDES_N 208 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
214 }; 209 };
215 }; 210 };
216 }; 211 };
217 ... 212 ...
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