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Linux/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt

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Diff markup

Differences between /Documentation/devicetree/bindings/phy/phy-miphy28lp.txt (Version linux-6.12-rc7) and /Documentation/devicetree/bindings/phy/phy-miphy28lp.txt (Version linux-5.9.16)


  1 STMicroelectronics STi MIPHY28LP PHY binding        1 STMicroelectronics STi MIPHY28LP PHY binding
  2 ============================================        2 ============================================
  3                                                     3 
  4 This binding describes a miphy device that is       4 This binding describes a miphy device that is used to control PHY hardware
  5 for SATA, PCIe or USB3.                             5 for SATA, PCIe or USB3.
  6                                                     6 
  7 Required properties (controller (parent) node)      7 Required properties (controller (parent) node):
  8 - compatible    : Should be "st,miphy28lp-phy"      8 - compatible    : Should be "st,miphy28lp-phy".
  9 - st,syscfg     : Should be a phandle of the s      9 - st,syscfg     : Should be a phandle of the system configuration register group
 10                   which contain the SATA, PCIe     10                   which contain the SATA, PCIe or USB3 mode setting bits.
 11                                                    11 
 12 Required nodes  :  A sub-node is required for      12 Required nodes  :  A sub-node is required for each channel the controller
 13                    provides. Address range inf     13                    provides. Address range information including the usual
 14                    'reg' and 'reg-names' prope     14                    'reg' and 'reg-names' properties are used inside these
 15                    nodes to describe the contr     15                    nodes to describe the controller's topology. These nodes
 16                    are translated by the drive     16                    are translated by the driver's .xlate() function.
 17                                                    17 
 18 Required properties (port (child) node):           18 Required properties (port (child) node):
 19 - #phy-cells    : Should be 1 (See second exam     19 - #phy-cells    : Should be 1 (See second example)
 20                   Cell after port phandle is d     20                   Cell after port phandle is device type from:
 21                         - PHY_TYPE_SATA            21                         - PHY_TYPE_SATA
 22                         - PHY_TYPE_PCI             22                         - PHY_TYPE_PCI
 23                         - PHY_TYPE_USB3            23                         - PHY_TYPE_USB3
 24 - reg           : Address and length of the re     24 - reg           : Address and length of the register set for the device.
 25 - reg-names     : The names of the register ad     25 - reg-names     : The names of the register addresses corresponding to the registers
 26                   filled in "reg". It can also     26                   filled in "reg". It can also contain the offset of the system configuration
 27                   registers used as glue-logic     27                   registers used as glue-logic to setup the device for SATA/PCIe or USB3
 28                   devices.                         28                   devices.
 29 - st,syscfg     : Offset of the parent configu     29 - st,syscfg     : Offset of the parent configuration register.
 30 - resets        : phandle to the parent reset      30 - resets        : phandle to the parent reset controller.
 31 - reset-names   : Associated name must be "mip     31 - reset-names   : Associated name must be "miphy-sw-rst".
 32                                                    32 
 33 Optional properties (port (child) node):           33 Optional properties (port (child) node):
 34 - st,osc-rdy            : to check the MIPHY0_     34 - st,osc-rdy            : to check the MIPHY0_OSC_RDY status in the glue-logic. This
 35                           is not available in      35                           is not available in all the MiPHY. For example, for STiH407, only the
 36                           MiPHY0 has this bit.     36                           MiPHY0 has this bit.
 37 - st,osc-force-ext      : to select the extern     37 - st,osc-force-ext      : to select the external oscillator. This can change from
 38                           different MiPHY insi     38                           different MiPHY inside the same SoC.
 39 - st,sata_gen           : to select which SATA     39 - st,sata_gen           : to select which SATA_SPDMODE has to be set in the SATA system config
 40                           register.                40                           register.
 41 - st,px_rx_pol_inv      : to invert polarity o     41 - st,px_rx_pol_inv      : to invert polarity of RXn/RXp (respectively negative line and positive
 42                           line).                   42                           line).
 43 - st,scc-on             : enable ssc to reduce     43 - st,scc-on             : enable ssc to reduce effects of EMI (only for sata or PCIe).
 44 - st,tx-impedance-comp  : to compensate tx imp     44 - st,tx-impedance-comp  : to compensate tx impedance avoiding out of range values.
 45                                                    45 
 46 example:                                           46 example:
 47                                                    47 
 48                 miphy28lp_phy: miphy28lp@9b220     48                 miphy28lp_phy: miphy28lp@9b22000 {
 49                         compatible = "st,miphy     49                         compatible = "st,miphy28lp-phy";
 50                         st,syscfg = <&syscfg_c     50                         st,syscfg = <&syscfg_core>;
 51                         #address-cells  = <1>;     51                         #address-cells  = <1>;
 52                         #size-cells     = <1>;     52                         #size-cells     = <1>;
 53                         ranges;                    53                         ranges;
 54                                                    54 
 55                         phy_port0: port@9b2200     55                         phy_port0: port@9b22000 {
 56                                 reg = <0x9b220     56                                 reg = <0x9b22000 0xff>,
 57                                       <0x9b090     57                                       <0x9b09000 0xff>,
 58                                       <0x9b040     58                                       <0x9b04000 0xff>;
 59                                 reg-names = "s     59                                 reg-names = "sata-up",
 60                                             "p     60                                             "pcie-up",
 61                                             "p     61                                             "pipew";
 62                                                    62 
 63                                 st,syscfg = <0     63                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 64                                 #phy-cells = <     64                                 #phy-cells = <1>;
 65                                 st,osc-rdy;        65                                 st,osc-rdy;
 66                                 reset-names =      66                                 reset-names = "miphy-sw-rst";
 67                                 resets = <&sof     67                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 68                         };                         68                         };
 69                                                    69 
 70                         phy_port1: port@9b2a00     70                         phy_port1: port@9b2a000 {
 71                                 reg = <0x9b2a0     71                                 reg = <0x9b2a000 0xff>,
 72                                       <0x9b190     72                                       <0x9b19000 0xff>,
 73                                       <0x9b140     73                                       <0x9b14000 0xff>;
 74                                 reg-names = "s     74                                 reg-names = "sata-up",
 75                                             "p     75                                             "pcie-up",
 76                                             "p     76                                             "pipew";
 77                                                    77 
 78                                 st,syscfg = <0     78                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 79                                                    79 
 80                                 #phy-cells = <     80                                 #phy-cells = <1>;
 81                                 st,osc-force-e     81                                 st,osc-force-ext;
 82                                 reset-names =      82                                 reset-names = "miphy-sw-rst";
 83                                 resets = <&sof     83                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 84                         };                         84                         };
 85                                                    85 
 86                         phy_port2: port@8f9500     86                         phy_port2: port@8f95000 {
 87                                 reg = <0x8f950     87                                 reg = <0x8f95000 0xff>,
 88                                       <0x8f900     88                                       <0x8f90000 0xff>;
 89                                 reg-names = "p     89                                 reg-names = "pipew",
 90                                             "u     90                                             "usb3-up";
 91                                                    91 
 92                                 st,syscfg = <0     92                                 st,syscfg = <0x11c 0x820>;
 93                                                    93 
 94                                 #phy-cells = <     94                                 #phy-cells = <1>;
 95                                 reset-names =      95                                 reset-names = "miphy-sw-rst";
 96                                 resets = <&sof     96                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 97                         };                         97                         };
 98                 };                                 98                 };
 99                                                    99 
100                                                   100 
101 Specifying phy control of devices                 101 Specifying phy control of devices
102 =================================                 102 =================================
103                                                   103 
104 Device nodes should specify the configuration     104 Device nodes should specify the configuration required in their "phys"
105 property, containing a phandle to the miphy de    105 property, containing a phandle to the miphy device node and an index
106 specifying which configuration to use, as desc    106 specifying which configuration to use, as described in phy-bindings.txt.
107                                                   107 
108 example:                                          108 example:
109                 sata0: sata@9b20000  {            109                 sata0: sata@9b20000  {
110                         ...                       110                         ...
111                         phys            = <&ph    111                         phys            = <&phy_port0 PHY_TYPE_SATA>;
112                         ...                       112                         ...
113                 };                                113                 };
114                                                   114 
115 Macro definitions for the supported miphy conf    115 Macro definitions for the supported miphy configuration can be found in:
116                                                   116 
117 include/dt-bindings/phy/phy.h                     117 include/dt-bindings/phy/phy.h
                                                      

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