1 STMicroelectronics STi MIPHY365x PHY binding 1 STMicroelectronics STi MIPHY365x PHY binding
2 ============================================ 2 ============================================
3 3
4 This binding describes a miphy device that is 4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA and PCIe. 5 for SATA and PCIe.
6 6
7 Required properties (controller (parent) node) 7 Required properties (controller (parent) node):
8 - compatible : Should be "st,miphy365x-phy" 8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array prop 9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
10 containing the miphy registe 10 containing the miphy registers and integer array should contain
11 an entry for each port sub-n 11 an entry for each port sub-node, specifying the control
12 register offset inside the s 12 register offset inside the sysconfig group.
13 13
14 Required nodes : A sub-node is required for 14 Required nodes : A sub-node is required for each channel the controller
15 provides. Address range inf 15 provides. Address range information including the usual
16 'reg' and 'reg-names' prope 16 'reg' and 'reg-names' properties are used inside these
17 nodes to describe the contr 17 nodes to describe the controller's topology. These nodes
18 are translated by the drive 18 are translated by the driver's .xlate() function.
19 19
20 Required properties (port (child) node): 20 Required properties (port (child) node):
21 - #phy-cells : Should be 1 (See second exam 21 - #phy-cells : Should be 1 (See second example)
22 Cell after port phandle is d 22 Cell after port phandle is device type from:
23 - PHY_TYPE_SATA 23 - PHY_TYPE_SATA
24 - PHY_TYPE_PCI 24 - PHY_TYPE_PCI
25 - reg : Address and length of regist 25 - reg : Address and length of register sets for each device in
26 "reg-names" 26 "reg-names"
27 - reg-names : The names of the register ad 27 - reg-names : The names of the register addresses corresponding to the
28 registers filled in "reg": 28 registers filled in "reg":
29 - sata: For SATA dev 29 - sata: For SATA devices
30 - pcie: For PCIe dev 30 - pcie: For PCIe devices
31 31
32 Optional properties (port (child) node): 32 Optional properties (port (child) node):
33 - st,sata-gen : Generation of locally 33 - st,sata-gen : Generation of locally attached SATA IP. Expected values
34 are {1,2,3). If not su 34 are {1,2,3). If not supplied generation 1 hardware will
35 be expected 35 be expected
36 - st,pcie-tx-pol-inv : Bool property to inver 36 - st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp)
37 - st,sata-tx-pol-inv : Bool property to inver 37 - st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp)
38 38
39 Example: 39 Example:
40 40
41 miphy365x_phy: miphy365x@fe382000 { 41 miphy365x_phy: miphy365x@fe382000 {
42 compatible = "st,miphy365 42 compatible = "st,miphy365x-phy";
43 st,syscfg = <&syscfg_rea 43 st,syscfg = <&syscfg_rear 0x824 0x828>;
44 #address-cells = <1>; 44 #address-cells = <1>;
45 #size-cells = <1>; 45 #size-cells = <1>;
46 ranges; 46 ranges;
47 47
48 phy_port0: port@fe382000 { 48 phy_port0: port@fe382000 {
49 reg = <0xfe382000 0x10 49 reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
50 reg-names = "sata", "p 50 reg-names = "sata", "pcie";
51 #phy-cells = <1>; 51 #phy-cells = <1>;
52 st,sata-gen = <3>; 52 st,sata-gen = <3>;
53 }; 53 };
54 54
55 phy_port1: port@fe38a000 { 55 phy_port1: port@fe38a000 {
56 reg = <0xfe38a000 0x10 56 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
57 reg-names = "sata", "p 57 reg-names = "sata", "pcie", "syscfg";
58 #phy-cells = <1>; 58 #phy-cells = <1>;
59 st,pcie-tx-pol-inv; 59 st,pcie-tx-pol-inv;
60 }; 60 };
61 }; 61 };
62 62
63 Specifying phy control of devices 63 Specifying phy control of devices
64 ================================= 64 =================================
65 65
66 Device nodes should specify the configuration 66 Device nodes should specify the configuration required in their "phys"
67 property, containing a phandle to the phy port 67 property, containing a phandle to the phy port node and a device type.
68 68
69 Example: 69 Example:
70 70
71 #include <dt-bindings/phy/phy.h> 71 #include <dt-bindings/phy/phy.h>
72 72
73 sata0: sata@fe380000 { 73 sata0: sata@fe380000 {
74 ... 74 ...
75 phys = <&phy_port0 PHY_TY 75 phys = <&phy_port0 PHY_TYPE_SATA>;
76 ... 76 ...
77 }; 77 };
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