1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/phy-roc 4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip USBDP Combo PHY with Samsung I 7 title: Rockchip USBDP Combo PHY with Samsung IP block
8 8
9 maintainers: 9 maintainers:
10 - Frank Wang <frank.wang@rock-chips.com> 10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com> 11 - Zhang Yubing <yubing.zhang@rock-chips.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 enum: 15 enum:
16 - rockchip,rk3588-usbdp-phy 16 - rockchip,rk3588-usbdp-phy
17 17
18 reg: 18 reg:
19 maxItems: 1 19 maxItems: 1
20 20
21 "#phy-cells": 21 "#phy-cells":
22 description: | 22 description: |
23 Cell allows setting the type of the PHY. 23 Cell allows setting the type of the PHY. Possible values are:
24 - PHY_TYPE_USB3 24 - PHY_TYPE_USB3
25 - PHY_TYPE_DP 25 - PHY_TYPE_DP
26 const: 1 26 const: 1
27 27
28 clocks: 28 clocks:
29 maxItems: 4 29 maxItems: 4
30 30
31 clock-names: 31 clock-names:
32 items: 32 items:
33 - const: refclk 33 - const: refclk
34 - const: immortal 34 - const: immortal
35 - const: pclk 35 - const: pclk
36 - const: utmi 36 - const: utmi
37 37
38 resets: 38 resets:
39 maxItems: 5 39 maxItems: 5
40 40
41 reset-names: 41 reset-names:
42 items: 42 items:
43 - const: init 43 - const: init
44 - const: cmn 44 - const: cmn
45 - const: lane 45 - const: lane
46 - const: pcs_apb 46 - const: pcs_apb
47 - const: pma_apb 47 - const: pma_apb
48 48
49 rockchip,dp-lane-mux: 49 rockchip,dp-lane-mux:
50 $ref: /schemas/types.yaml#/definitions/uin 50 $ref: /schemas/types.yaml#/definitions/uint32-array
51 minItems: 2 51 minItems: 2
52 maxItems: 4 52 maxItems: 4
53 items: 53 items:
54 maximum: 3 54 maximum: 3
55 description: 55 description:
56 An array of physical Type-C lanes indexe 56 An array of physical Type-C lanes indexes. Position of an entry
57 determines the DisplayPort (DP) lane ind 57 determines the DisplayPort (DP) lane index, while the value of an entry
58 indicates physical Type-C lane. The supp 58 indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
59 e.g. for 2 lanes DP lanes map, we could 59 e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
60 3>;", assuming DP lane0 on Type-C phy la 60 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
61 lane3. For 4 lanes DP lanes map, we coul 61 lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
62 <0, 1, 2, 3>;", assuming DP lane0 on Typ 62 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
63 phy lane1, DP lane2 on Type-C phy lane2, 63 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
64 DP lanes are mapped by DisplayPort Alt m 64 DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
65 65
66 rockchip,u2phy-grf: 66 rockchip,u2phy-grf:
67 $ref: /schemas/types.yaml#/definitions/pha 67 $ref: /schemas/types.yaml#/definitions/phandle
68 description: 68 description:
69 Phandle to the syscon managing the 'usb2 69 Phandle to the syscon managing the 'usb2 phy general register files'.
70 70
71 rockchip,usb-grf: 71 rockchip,usb-grf:
72 $ref: /schemas/types.yaml#/definitions/pha 72 $ref: /schemas/types.yaml#/definitions/phandle
73 description: 73 description:
74 Phandle to the syscon managing the 'usb 74 Phandle to the syscon managing the 'usb general register files'.
75 75
76 rockchip,usbdpphy-grf: 76 rockchip,usbdpphy-grf:
77 $ref: /schemas/types.yaml#/definitions/pha 77 $ref: /schemas/types.yaml#/definitions/phandle
78 description: 78 description:
79 Phandle to the syscon managing the 'usbd 79 Phandle to the syscon managing the 'usbdp phy general register files'.
80 80
81 rockchip,vo-grf: 81 rockchip,vo-grf:
82 $ref: /schemas/types.yaml#/definitions/pha 82 $ref: /schemas/types.yaml#/definitions/phandle
83 description: 83 description:
84 Phandle to the syscon managing the 'vide 84 Phandle to the syscon managing the 'video output general register files'.
85 When select the DP lane mapping will req 85 When select the DP lane mapping will request its phandle.
86 86
87 sbu1-dc-gpios: 87 sbu1-dc-gpios:
88 description: 88 description:
89 GPIO connected to the SBU1 line of the U 89 GPIO connected to the SBU1 line of the USB-C connector via a big resistor
90 (~100K) to apply a DC offset for signall 90 (~100K) to apply a DC offset for signalling the connector orientation.
91 maxItems: 1 91 maxItems: 1
92 92
93 sbu2-dc-gpios: 93 sbu2-dc-gpios:
94 description: 94 description:
95 GPIO connected to the SBU2 line of the U 95 GPIO connected to the SBU2 line of the USB-C connector via a big resistor
96 (~100K) to apply a DC offset for signall 96 (~100K) to apply a DC offset for signalling the connector orientation.
97 maxItems: 1 97 maxItems: 1
98 98
99 orientation-switch: 99 orientation-switch:
100 description: Flag the port as possible han 100 description: Flag the port as possible handler of orientation switching
101 type: boolean 101 type: boolean
102 102
103 mode-switch: 103 mode-switch:
104 description: Flag the port as possible han 104 description: Flag the port as possible handler of altmode switching
105 type: boolean 105 type: boolean
106 106
107 port: 107 port:
108 $ref: /schemas/graph.yaml#/properties/port 108 $ref: /schemas/graph.yaml#/properties/port
109 description: 109 description:
110 A port node to link the PHY to a TypeC c 110 A port node to link the PHY to a TypeC controller for the purpose of
111 handling orientation switching. 111 handling orientation switching.
112 112
113 required: 113 required:
114 - compatible 114 - compatible
115 - reg 115 - reg
116 - clocks 116 - clocks
117 - clock-names 117 - clock-names
118 - resets 118 - resets
119 - reset-names 119 - reset-names
120 - "#phy-cells" 120 - "#phy-cells"
121 121
122 additionalProperties: false 122 additionalProperties: false
123 123
124 examples: 124 examples:
125 - | 125 - |
126 #include <dt-bindings/clock/rockchip,rk358 126 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
127 #include <dt-bindings/reset/rockchip,rk358 127 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
128 128
129 usbdp_phy0: phy@fed80000 { 129 usbdp_phy0: phy@fed80000 {
130 compatible = "rockchip,rk3588-usbdp-phy" 130 compatible = "rockchip,rk3588-usbdp-phy";
131 reg = <0xfed80000 0x10000>; 131 reg = <0xfed80000 0x10000>;
132 #phy-cells = <1>; 132 #phy-cells = <1>;
133 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_R 133 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
134 <&cru CLK_USBDP_PHY0_IMMORTAL>, 134 <&cru CLK_USBDP_PHY0_IMMORTAL>,
135 <&cru PCLK_USBDPPHY0>, 135 <&cru PCLK_USBDPPHY0>,
136 <&u2phy0>; 136 <&u2phy0>;
137 clock-names = "refclk", "immortal", "pcl 137 clock-names = "refclk", "immortal", "pclk", "utmi";
138 resets = <&cru SRST_USBDP_COMBO_PHY0_INI 138 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
139 <&cru SRST_USBDP_COMBO_PHY0_CMN 139 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
140 <&cru SRST_USBDP_COMBO_PHY0_LAN 140 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
141 <&cru SRST_USBDP_COMBO_PHY0_PCS 141 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
142 <&cru SRST_P_USBDPPHY0>; 142 <&cru SRST_P_USBDPPHY0>;
143 reset-names = "init", "cmn", "lane", "pc 143 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
144 rockchip,u2phy-grf = <&usb2phy0_grf>; 144 rockchip,u2phy-grf = <&usb2phy0_grf>;
145 rockchip,usb-grf = <&usb_grf>; 145 rockchip,usb-grf = <&usb_grf>;
146 rockchip,usbdpphy-grf = <&usbdpphy0_grf> 146 rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
147 rockchip,vo-grf = <&vo0_grf>; 147 rockchip,vo-grf = <&vo0_grf>;
148 }; 148 };
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