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Linux/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml

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Diff markup

Differences between /Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml (Version linux-6.12-rc7) and /Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml (Version linux-5.18.19)


  1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C      1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2 %YAML 1.2                                           2 %YAML 1.2
  3 ---                                                 3 ---
  4 $id: http://devicetree.org/schemas/phy/phy-teg !!   4 $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
  5 $schema: http://devicetree.org/meta-schemas/co !!   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
  6                                                     6 
  7 title: NVIDIA Tegra194 & Tegra234 P2U          !!   7 title: NVIDIA Tegra194 P2U binding
  8                                                     8 
  9 maintainers:                                        9 maintainers:
 10   - Thierry Reding <treding@nvidia.com>             10   - Thierry Reding <treding@nvidia.com>
 11                                                    11 
 12 description: >                                     12 description: >
 13   Tegra194 has two PHY bricks namely HSIO (Hig     13   Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
 14   Speed) each interfacing with 12 and 8 P2U in     14   Speed) each interfacing with 12 and 8 P2U instances respectively.
 15   Tegra234 has three PHY bricks namely HSIO, N << 
 16   each interfacing with 8, 8 and 8 P2U instanc << 
 17   A P2U instance is a glue logic between Synop     15   A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
 18   interface and PHY of HSIO/NVHS/GBE bricks. E !!  16   interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
 19   PCIe lane.                                   !!  17   lane.
 20                                                    18 
 21 properties:                                        19 properties:
 22   compatible:                                      20   compatible:
 23     enum:                                      !!  21     const: nvidia,tegra194-p2u
 24       - nvidia,tegra194-p2u                    << 
 25       - nvidia,tegra234-p2u                    << 
 26                                                    22 
 27   reg:                                             23   reg:
 28     maxItems: 1                                    24     maxItems: 1
 29     description: Should be the physical addres     25     description: Should be the physical address space and length of respective each P2U instance.
 30                                                    26 
 31   reg-names:                                       27   reg-names:
 32     items:                                         28     items:
 33       - const: ctl                                 29       - const: ctl
 34                                                << 
 35   nvidia,skip-sz-protect-en:                   << 
 36     description: Should be present if two PCIe << 
 37       the root port and its immediate downstre << 
 38     type: boolean                              << 
 39                                                    30 
 40   '#phy-cells':                                    31   '#phy-cells':
 41     const: 0                                       32     const: 0
 42                                                    33 
 43 additionalProperties: false                        34 additionalProperties: false
 44                                                    35 
 45 examples:                                          36 examples:
 46   - |                                              37   - |
 47     p2u_hsio_0: phy@3e10000 {                      38     p2u_hsio_0: phy@3e10000 {
 48         compatible = "nvidia,tegra194-p2u";        39         compatible = "nvidia,tegra194-p2u";
 49         reg = <0x03e10000 0x10000>;                40         reg = <0x03e10000 0x10000>;
 50         reg-names = "ctl";                         41         reg-names = "ctl";
 51                                                    42 
 52         #phy-cells = <0>;                          43         #phy-cells = <0>;
 53     };                                             44     };
                                                      

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