1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,us
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Qualcomm Synopsys DesignWare Core 28nm
8
9 maintainers:
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.or
11
12 description: |
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28n
14
15 properties:
16 compatible:
17 enum:
18 - qcom,usb-hs-28nm-femtophy
19
20 reg:
21 maxItems: 1
22
23 "#phy-cells":
24 const: 0
25
26 clocks:
27 items:
28 - description: rpmcc ref clock
29 - description: PHY AHB clock
30 - description: Rentention clock
31
32 clock-names:
33 items:
34 - const: ref
35 - const: ahb
36 - const: sleep
37
38 resets:
39 items:
40 - description: PHY core reset
41 - description: POR reset
42
43 reset-names:
44 items:
45 - const: phy
46 - const: por
47
48 vdd-supply:
49 description: phandle to the regulator VDD
50
51 vdda1p8-supply:
52 description: phandle to the regulator 1.8V
53
54 vdda3p3-supply:
55 description: phandle to the regulator 3.3V
56
57 required:
58 - compatible
59 - reg
60 - "#phy-cells"
61 - clocks
62 - clock-names
63 - resets
64 - reset-names
65 - vdd-supply
66 - vdda1p8-supply
67 - vdda3p3-supply
68
69 additionalProperties: false
70
71 examples:
72 - |
73 #include <dt-bindings/clock/qcom,gcc-qcs40
74 #include <dt-bindings/clock/qcom,rpmcc.h>
75 usb2_phy_prim: phy@7a000 {
76 compatible = "qcom,usb-hs-28nm-femtoph
77 reg = <0x0007a000 0x200>;
78 #phy-cells = <0>;
79 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
80 <&gcc GCC_USB_HS_PHY_CFG_AHB_
81 <&gcc GCC_USB2A_PHY_SLEEP_CLK
82 clock-names = "ref", "ahb", "sleep";
83 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_
84 <&gcc GCC_USB2A_PHY_BCR>;
85 reset-names = "phy", "por";
86 vdd-supply = <&vreg_l4_1p2>;
87 vdda1p8-supply = <&vreg_l5_1p8>;
88 vdda3p3-supply = <&vreg_l12_3p3>;
89 };
90 ...
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