1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/phy/rockchi 4 $id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip SoC HDMI/eDP Transmitter Combo 7 title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
8 8
9 maintainers: 9 maintainers:
10 - Cristian Ciocaltea <cristian.ciocaltea@coll 10 - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
11 11
12 properties: 12 properties:
13 compatible: 13 compatible:
14 enum: 14 enum:
15 - rockchip,rk3588-hdptx-phy 15 - rockchip,rk3588-hdptx-phy
16 16
17 reg: 17 reg:
18 maxItems: 1 18 maxItems: 1
19 19
20 clocks: 20 clocks:
21 items: 21 items:
22 - description: Reference clock 22 - description: Reference clock
23 - description: APB clock 23 - description: APB clock
24 24
25 clock-names: 25 clock-names:
26 items: 26 items:
27 - const: ref 27 - const: ref
28 - const: apb 28 - const: apb
29 29
30 "#clock-cells": <<
31 const: 0 <<
32 <<
33 "#phy-cells": 30 "#phy-cells":
34 const: 0 31 const: 0
35 32
36 resets: 33 resets:
37 items: 34 items:
38 - description: PHY reset line 35 - description: PHY reset line
39 - description: APB reset line 36 - description: APB reset line
40 - description: INIT reset line 37 - description: INIT reset line
41 - description: CMN reset line 38 - description: CMN reset line
42 - description: LANE reset line 39 - description: LANE reset line
43 - description: ROPLL reset line 40 - description: ROPLL reset line
44 - description: LCPLL reset line 41 - description: LCPLL reset line
45 42
46 reset-names: 43 reset-names:
47 items: 44 items:
48 - const: phy 45 - const: phy
49 - const: apb 46 - const: apb
50 - const: init 47 - const: init
51 - const: cmn 48 - const: cmn
52 - const: lane 49 - const: lane
53 - const: ropll 50 - const: ropll
54 - const: lcpll 51 - const: lcpll
55 52
56 rockchip,grf: 53 rockchip,grf:
57 $ref: /schemas/types.yaml#/definitions/pha 54 $ref: /schemas/types.yaml#/definitions/phandle
58 description: Some PHY related data is acce 55 description: Some PHY related data is accessed through GRF regs.
59 56
60 required: 57 required:
61 - compatible 58 - compatible
62 - reg 59 - reg
63 - clocks 60 - clocks
64 - clock-names 61 - clock-names
65 - "#phy-cells" 62 - "#phy-cells"
66 - resets 63 - resets
67 - reset-names 64 - reset-names
68 - rockchip,grf 65 - rockchip,grf
69 66
70 additionalProperties: false 67 additionalProperties: false
71 68
72 examples: 69 examples:
73 - | 70 - |
74 #include <dt-bindings/clock/rockchip,rk358 71 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
75 #include <dt-bindings/reset/rockchip,rk358 72 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
76 73
77 soc { 74 soc {
78 #address-cells = <2>; 75 #address-cells = <2>;
79 #size-cells = <2>; 76 #size-cells = <2>;
80 77
81 phy@fed60000 { 78 phy@fed60000 {
82 compatible = "rockchip,rk3588-hdptx-ph 79 compatible = "rockchip,rk3588-hdptx-phy";
83 reg = <0x0 0xfed60000 0x0 0x2000>; 80 reg = <0x0 0xfed60000 0x0 0x2000>;
84 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_ 81 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
85 clock-names = "ref", "apb"; 82 clock-names = "ref", "apb";
86 #phy-cells = <0>; 83 #phy-cells = <0>;
87 resets = <&cru SRST_HDPTX0>, <&cru SRS 84 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
88 <&cru SRST_HDPTX0_INIT>, <&cr 85 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
89 <&cru SRST_HDPTX0_LANE>, <&cr 86 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
90 <&cru SRST_HDPTX0_LCPLL>; 87 <&cru SRST_HDPTX0_LCPLL>;
91 reset-names = "phy", "apb", "init", "c 88 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
92 rockchip,grf = <&hdptxphy_grf>; 89 rockchip,grf = <&hdptxphy_grf>;
93 }; 90 };
94 }; 91 };
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